Image Processing System Based on tms320dm2.

Image Processing System Based on tms320dm2.

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Source: China Power Grid Author: Yan Ning, Yu yunqi

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1 Introduction

With the rapid development of large-scale integrated circuits, DSP performance is becoming more and more perfect and can meet the real-time requirements for data processing speed during image processing. An image processing system built with DSP as the core processor is widely used. Its advantages include abundant DSP resources, flexible programming, simple algorithm design, and modular design in system software development, it can improve the universality of the system and shorten the development cycle of the system. This article introduces an image processing system based on tms320dm64.

2 Introduction

It is a DSP developed by TI for network and multimedia applications. The main features are as follows:

The CPU has a high clock frequency and has three clock rates: 500 MHz, 600 MHz, and 720 MHz (the clock rate designed in this system is 600 MHz );

Dedicated video ports, including three configurable video ports;

External interface: 64 independent channel enhanced EDMA controller, multi-channel audio serial port (McASP), 64-bit external storage unit interface EMIF, 66 MHz 32-bit, 3.3 v pci Master/Slave interface, 10 Mb/s/100 Mb/s Ethernet port (EMAC), General I/O port (GPIO) and other peripheral interfaces;

Dedicated cache can accelerate data storage and computation. TMS320DM64 adopts the Cache structure of level-2 high-speed Cache. The level-1 program and data Cache are 16 KB, And the level-2 Cache is 256 KB. Its CPU kernel is based on the CPU of C64X.

Therefore, the processing speed and peripheral interfaces of tms320dm64are high, and a dedicated video port is provided. Compared with other products with the same performance, the price-performance ratio of the image processing system is high. In terms of product performance and economic benefits, the image processing system is ideal.

3 System Design

3.1 Hardware Design

The system hardware architecture Diagram 1 is shown in. The system processes the image data input by the video input device camera, decoded by the video decoder, and transmitted to the tms320dm642. the system stores and processes the collected data, the processed data is sent to the video encoder, Which is encoded and then sent to the video output device monitor.

3.2 video input Design

Video Decoder is a specialized video decoder used to capture images from video input devices (cameras). The video decoder is used to drive image acquisition. This simplifies the design and saves design time and shortens the design cycle. The Video Decoder uses SAA7115 from Phillips.

The data collection driver of TMS320DM6412 is designed based on the IOM driver mode. The drive design is divided into two layers: Class Driver and Mini-Driver. The FVID module is used to design Class Driver, which provides independent and General API settings and a variety of Mini-Driver services. To maximize the code reuse rate, the Mini-Driver is divided into two parts: general and individual parts for different circuit boards. The former uses EDMAs and video ports for data transmission, the latter is also called the EDC (External DeviceControl) interface design. It is used to set Video Decoder for different circuit boards, including video encoder initialization and configuration. When you use this method to design the Input drive of the video on the video, you must configure the DSP/BIOS parameters: correctly configure the User-DefinedDrivers item in DeviceDrivers under the Input/Output, including Init function, Function table ptr, Function table type, Deviceid, Device params ptr, Device global data ptr, and other parameters. After the DSP/BIOS parameters are configured, the DSP program contains the vport. h. vportcap. h, saa7115.h, and initialize and configure SAA7115. The video data input directly calls the API functions supported by the device to complete the video input driver design.

3.3 video output design video output encoder uses Phillips SAA7105. SAA7105 and SAA7115 are a pair of devices. Figure 3 shows the video output drive diagram during the display operation. The data is loaded from the memory to the frame buffer, and then transmitted to the video port FIFO through EDMA. The video port then transmits the data to the video encoder for display. An EDMA interrupt is triggered after each frame of data is loaded from the storage. This interrupt is used to manage frame buffers and reload and update data by EDMA.

The video output driver design is similar to the video input Driver Design. After the parameters in DSP/BIOS are configured, the DSP program contains the vport. h, vportdis. h, saa7105.h, and initialize and configure SAA7105. Video data output directly calls the API functions supported by the device to complete the video output driver design.

3.4 Data Processing Design

The data processing design consists of two steps: Step 1: Determine the algorithm, and Step 2: Use the DSP program code to implement the algorithm. The algorithm is implemented using powerful and easy-to-use Matlab software. The algorithm is designed and simulated in the Matlab environment. After the simulation results are correct, the algorithm can be determined. The DSP code is designed according to the C6000 series code development process shown in Figure 4. The code development process is divided into three stages: the first stage produces C code, the second stage optimizes C code, and the third stage is compiled to convert C code into linear assembly or assembly code and optimize it, until the program code meets the requirements.

In the whole design, code optimization is the core. Only by optimizing the code efficiency can we ensure that it meets the established requirements. Code optimization steps and methods:

1) set the compilation optimization level to-o3 in the CCS programming environment, and perform some manual preliminary Optimization on the Code according to the optimization rules of the C code.

2) When the efficiency of the optimized C Code fails to meet the requirements, the C code is converted to linear assembly code for further optimization by the compiler.

3) if the requirements are not met, the linear assembly code is converted into assembly code, and the code sequence is adjusted manually to change the parallel and streamline capabilities of the Code, by constantly adjusting the code, the code execution efficiency can meet the requirements.

4. Application Instances

The hardware platform of TMS320DM642EVM is used to rotate an image in the PAL format. During algorithm design, the interpolation algorithm adopts the nearest interpolation algorithm. The whole software is written in C language, and the program running result is not ideal, and the image is obviously stuck. The Code part of the most time-consuming Rotation Algorithm is converted into assembly code, optimized for it, re-adjusted the code order, and added the code parallel and streamline capabilities, greatly improving the code execution efficiency, the program runs smoothly without being stranded, and the running speed meets real-time requirements.

5 conclusion

The dedicated video port provided by tms320dm64is used to transmit data through EDMAs to make video acquisition and output very simple. The video driver design mode supported by tms320dm64greatly simplifies the workload of video input/output driver design, this simplifies the design of the entire image processing system, saves the design time, and ensures the efficiency of the system design. The image processing system based on tms320dm64is easy to design and has a short design cycle. Therefore, it is an ideal choice for image processing systems.