Intel CPU Overview-from 8086 to quad Core i7

Source: Internet
Author: User
Tags comparison table intel pentium

Now Intel has become synonymous with CPUs, but Intel did not now. From the 8,086-2013-year-old i7, released in 1978, for 35 years, she witnessed a number of changes from PC to internet and mobile Internet, many of which have changed over the years. This article does not intend to the history and lead the history of the man to do how much description and evaluation (this content is enough to write several books), if you are more interested in these content, please visit. This article only gives a brief introduction to several prominent figures in the Intel CPU family and contrasts them.

Brief History

Next, a brief introduction to several of Intel's epoch-making CPU products.

Intel? 8086 (16-bit, 1978)

This is a 1978 release of the CPU products, it is the elder of the Intel family. The 1970s of things, why should introduce it? Because I like many classmates, the university also must learn this kind of ancient thing. When I was in this class, I was wondering why I had to learn something so old. Later on Intel's other CPUs know, the more CPU power, the more complex, of course, a semester can not finish, of course, these are something.

Before 8086, there is a small well-known 8-bit CPU product--8088, but its impact on later products is far from 8086 big, so this article does not introduce him.

Take a look at the "new features" of 8086:

Take a look at some of the "worth mentioning":

    • Direct memory addressing capacity up to 1MB
    • Clock frequency 5 m, 8M, 10MHz
    • The last one says: There are 40-lead ceramic and plastic packages

The last sentence of the last paragraph is worth noting: 8086 can be achieved with multiple processors for high performance.

The IA-32 series architecture has evolved from 8086 of such 16-bit processors. 8086 has 16-bit registers, 16-bit external data bus, and 20-bit data buses, which provide 1M byte addressing capability, 1m=2^20.

8086 introduce the concept of "Duan" into the IA-32 architecture. Due to the introduction of the segment, a 16-bit segment register holds a pointer to 64K bytes of memory. The 20-bit address can provide 1M byte addressing capability via a segment register and an additional 16-bit pointer.

Intel? 286 Processors (1982)

The Intel286 processor introduces "Protected mode" to the IA-32. Protected mode uses the contents of the segment register as a pointer pointer to a selector or to a table of descriptors (descriptor). The descriptor provides a 24-bit base address, which increases the physical memory addressing capability to 16M bytes (16m=2^24) and supports segment-switched-based virtual memory management, as well as protection mechanisms for some columns. These mechanisms include:

    • Segment boundary Check
    • Read only and execute segment options only
    • Four levels of privilege

The clock frequency is from 6MHz to 20MHz.

The Intel386? Processor (1985)

The Intel386 processor is the first 32-bit processor in the IA-32 architecture family. It includes 32-bit registers that can hold the operand and can be used for addressing. The low half of each 32-bit register retains the functionality of the previous series of 16-bit registers, allowing for back compatibility (compatible with past executable code). The processor also provides virtual 8086 mode to allow efficient execution of programs created for 8086/8088.

In addition, the INTEL386 processor also supports:

    • 32-bit address bus supporting up to 4G of physical memory
    • Segmented (segmented) memory mode and flat (flat) memory mode
    • Paging, 4k-sized pages provide a way to "virtual memory management"
    • Support for parallel stages (should mean that the instruction executes several stages can be parallel)

Clock frequency is 12.5MHz

Intel?486 Processor (1989)

The Intel486 processor enhances the execution of instructions by extending the 386-processor instruction decoder (instruction decode) and the Execution unit (execution uint) to 5 queueing stages (pipelined stage). The operation of each phase is performed at the same time as the different phases of the other directives.

In addition, the processor introduces the following:

    • 8k on-chip cache, which increases the number of instruction executions per unit of time.
    • Integrated x87 floating point Compute Unit (FPU)
    • Power-saving mode and system management capabilities

The clock frequency is from 25M to 50M.

Intel? Pentium? Processors (1993)

The Intel Pentium processor joins the second execution pipeline (pipeline) for more robust performance (two pipelines, well-known U and V pipelines that can execute two instructions in the same clock cycle). The on-chip cache doubles (16K), 8k is used to cache the code, and 8k is used to cache the data. The data cache uses the MESI protocol with the INTEL486 processor to support more efficient cache write-back. An on-chip branch table and is added to enhance the performance of the loop execution.

In addition, the processor joins the following:

    • Some extensions make the virtual 8086 mode more efficient and allow 4M bytes or 4 K-byte paging
    • 128-bit and 256-bit internal data paths are used to prompt for internal data transfer
    • The enhanced external data bus is increased to 64 bits
    • APIC (Advanced Programmable Interrupt Controller, high-level programmable interrupt Controller) to support systems that can use multicore
    • Dual-core mode to support dual-core systems without gluing (external controller coordination)

Another important phase of the results is the Pentium family introduced Intel MMX technology, Intel MMX technology uses the single instruction multi-data (Single-instruction multiple-data, SIMD) execution mode to achieve parallel computing on the packaged 64 register.

The clock frequency is from the original 60Mhz and 66Mhz to the later 200MHz

Intel? Pentium? 4 Processor Family (2000-2006)

PS: This six years for the CPU of the world, the transformation is too fast, "ever-changing" seems to have not enough to describe the CPU changes over the years.

The Intel Pentium 4 processor family is based on the Intel NetBurst Micro-architecture. The Pentium 4 processor introduces SSME2 (streaming SIMD Extension 2).

The Pentium 4 processor has a 3.4GHz frequency and supports Hyper-Threading Technology (hyper-threading technology).

The Intel 64 architecture was introduced in the Pentium 4 processor 6xx and 5XX series.

Intel? Virtualization Technology (Intel?) VT) is introduced in Pentium 4 processors 672 and 662.

Ben 4 Series has approached the limits of CPU frequency technology, which makes the "Moore Law" of the year no longer useful.

I'll just make a few brief descriptions of the following.

Intel? Xeon? Processor (2001-2007) Intel Xeon series, the family was originally IA32 architecture, and later the product used more Intel64, the family is designed for multicore high-performance servers and workstations.
Intel? The Core? Duo and Intel? The Core? Solo processors (2006-2007) This series is Intel's design for low-power CPU products, mainly used in laptops at that time (the notebook market grew rapidly, a big replacement for the PC).
Intel? Xeon? Processor 5200, 5400, 7400 Series and Intel? Core?2 Processor Family (2007) to the strong new series of products, is still "tall on" the service-side route, based on the new 45nm architecture.
Intel? Atom? Processor Family Atom Architecture, 45nm technology, is also designed for low power consumption, most used in mobile devices (mobile phones, tablets, etc.). It was the timing of the smartphone's rise, although the market's eldest was Nokia (S60 already known as a smartphone).
Intel? Core?i7 Processor Family (2008)

Nehalem architecture, 45nm. With Atom at the same time the core I series, this is also the "household name" of the product.

Intel? Xeon? Processor 7500 Series (2010)

Nehalem architecture, 45nm. Continue on the tall.

Second Generation Intel? The Core? Processor Family (2011)

Sandy Bridge Architecture, 32nm. The second generation of the core I series, I now use the i2410 is this series.

Third Generation Intel? The Core? Processor Family (2012)

Ivy Bridge Architecture, and some of the Ivy Bridge-ep architectures.

Fourth Generation Intel? The Core? Processor Family (2013)

Haswell architecture.

"Three Delegates"

Here we need to point out three machines representing the CPU, they are 8086,386 (IA32) and Core i7 (INTEL64).

8086CPU Architecture

8086 compared to the subsequent CPU is much simpler, which is why the textbook likes to take him to say the reason. Let me get a glimpse of the architecture of 8086 (left). closely related to the architecture is its pin package, Yes, he has the same 40-pin package as the 51 single-chip microcomputer (right).

Basic execution Environment

The architecture and encapsulation are not our concern for the ape of the program, and we only care about our code. Until now, the specific CPU-related code will still be written in assembly language, the natural concern is the register; on top 8086

The schema diagram (left) can be seen in the segment register (Segment register) and instruction pointer (instruction pointer).

8086 of the registers are very few, less than one picture can summarize all registers:

Where IP is the instruction pointer, flags is the machine state word. Where Cs,ds,ss,es is a four-segment register, SP and BP are data pointer, and Si and di are indexed registers (index register).

The IA32 register is a bit more:

Because it has a built-in FPU (floating point Compute Unit), MMX (multimedia Enhancement) and XMM (SSE-related), in addition to the basic execution link.

The IA32 instruction pointer and machine status word are called EIP and EFlags respectively.


8 32 for Register: EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP

6 Segment Registers: CS, DS, SS, ES, FS, GS

The Intel 64 execution environment is similar to the IA32 environment:

Intel 64 's general-purpose registers were increased to 16, namely:RAX, RBX, RCX, RDX, RSI, RDI, RSP, RBP, R8~r15


The IA32 can be compatible with 8086, and 8086 of the programs can run on IA32, which relies on register and instruction compatibility. This was a good market for Intel at the time, just imagine, if the 386 is not compatible with DOS, there is no estimate of today's Microsoft.

The same Intel 64 is also compatible with IA32, below is a comparison table:

Memory model

Next, briefly describe the 8086,IA-32 and Intel 64 memory models.

8086 has a 20-bit address bus, but the register is 16-bit, which seems to inevitably lead to a segmented memory model. The Code Snippet Register (CS) and instruction Pointer (IP) point to the code that is currently executing, and the data segment Register (DS) or other segment register is used in conjunction with the index register to locate the data in memory.

IA32 memory model

IA32 era, virtual memory technology has been supported by the CPU, which is the emergence of three kinds of memory models:

A flat memory model in which memory behaves as a single contiguous address space, also called a linear address space.

segmented memory model , in which memory is represented as a series of separate address spaces that become segments, code snippets, data segments, stacks (stack) segments are typical separate segments. The program addresses a byte with a logical address. All segments of the system are mapped to the processor's linear address space, and the processor is responsible for translating the logical address and the linear address into each other. This conversion is transparent to the application.

Real address mode , which is used for the Intel 8086 processor. It is intended to allow the program to run on a 8086 processor.

Several modes are as follows:

Paging vs. virtual memory

In the flat and segmented memory models, the linear address space is mapped directly (or paged) to the physical address space of the processor.

When using direct mapping (close paging), each of the antecedent addresses has a one-to-one physical address corresponding to it. The linear address is sent directly from the processor's address bus, without any conversion required.

When using the paging mechanism of the IA-32 schema (when paging is turned on), the linear address space is divided into a series of pages and mapped to virtual addresses, and subsequent pages of the virtual memory map the corresponding physical memory as needed. The paging mechanism is transparent to the application when the page is used by the operating system or an executable program. All applications look at the linear address space.

In addition, the paging mechanism of IA-32 includes some extension functions:

    • Physical Address Extensions (PAE, Physical Address Extensions for addressing addresses that exceed 4G
    • The page size extension (pse,page size Extensions) is used to map a 4M byte linear address page to a physical address.

Extended read this article is just an overview (or introduction) of the Intel series CPUs, read the Intel Developer's Manual "3" for more details.

"1" CPU Development history: Intel (Intel Corporation),

"2"Intel 8086 6-bit HMOS microprocessor 8086/8086-2/8086-1,

"3"Intel IA-32 architectures software Developer ' s Manual, Processors/architectures-software-developer-manuals.html

Intel CPU Overview-from 8086 to quad Core i7

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