Interface Design between large-capacity nor flash and 8-Bit Single-Chip Microcomputer

Introduction

Flash Memory, also known as flash memory, is a new kind of non-volatile semiconductor storage developed in the late 1980s S. It has the features of Ram and Rom, which can be erased and rewritten online, and keep data intact after power loss.

Nor flash is the first kind of flash memory. Compared with other types of flash memory, nor flash has the following advantages: high reliability, fast random reading speed, and single-byte or single-word programming, allows the CPU to directly read code from the chip for execution. Therefore, nor flash memory plays an important role in embedded system application development. This paper takes SST company's nor flash chip sst39sf040 and MCS-51 single-chip microcomputer as an example, in view of the special application of large capacity norflash in 8-bit low-end single-chip microcomputer, the interface hardware and interface software design method is introduced in detail.

1 sst39sf040 chip Introduction

Sst39sf040 is a kind of nor flash memory recently launched by SST Based on superflash technology. It belongs to the parallel flash memory series of SST; suitable for scenarios where applications need to write data online or store large volumes of non-volatile data repeatedly.

Internal function structure and external pins of the 1.1 Chip

Figure 1 shows the internal function structure of sst39sf040, it consists of super-flash storage units, row decoders, column decoders, address buffering and latches, input/output buffering, data latches, and control logic circuits. Figure 2 shows the external pin distribution, in which A18 ~ A0 is the address line, CE is the chip signal, oe can be used as the reading signal, we is the writing signal, dq7 ~ Dq0 is the data line.

Key features of the 1.2 Chip

① The capacity is 512 KB, which is organized by kb × 8 bits.

② A single 5 V power supply is used, and the programmed Power Supply VPP is generated inside the chip.

③ The chip can be repeatedly erased for 100 times, and the data is stored on May 1, 100.

④ The typical operating current value is 10 Ma, and the typical standby current value is 30 μA.

⑤ Sector structure: the size of the slice is 4 kb.

⑥ Typical values of read, erase, and byte programming time: the data read time is 45 ~ 70 ns; Sector erasure time is 18 MS, the whole part erasure time is 70 MS; byte programming time is 14 μs.

7 There are status signs that record the internal erasure operation and the completion of programming write operations.

⑧ Provides hardware and software data protection functions.

⑨ Has the address and data lock functions.

1.3 chip operation

1.3.1 software operation command sequence of the chip

Software operations of sst39sf040 can be divided into two types: Common read operations and command operations.

The common read operation is very simple. It is similar to the ram read operation. When the OE and Ce signals are low at the same time, the data can be read from the chip.

Command operations on the chip include Chip identification, byte programming, sector erasure, and whole-disk erasure. These operations are completed by their respective software operation command sequences, as listed in table 1. Where, BA is the address of the bytes to be programmed, data is the byte programming data, and sax is the address of the slice to be erased. The address in the command is only valid for 15 characters, and the 4 characters in height can be set to "0" or "1 ".

The software operation command sequence of sst39sf040 is actually composed of one or more bus write operations. Take the sst39sf040 sector erasure as an example. The operation process consists of three steps: Step 1, enable the erasure method, and use the bus write operation between 1st and 1st cycles as shown in Table 1; step 2: load the fan area erasure command (30 h) and the address of the slice to be erased, and use the corresponding 2nd-cycle bus write operation. Step 3: perform an internal erasure. The maximum internal erasure time is 25 ms.

During bus write operations, oe must be kept at a high level, CE and we should be at a low level. The address and data lock are controlled by the edges of the CE and we signals. The falling edges that appear later will lock the address, and the first rising edges will lock the data.

1.3.2 status detection for byte programming and erasure operations

It takes some time for the chip to perform internal byte programming or erasure operations. Although a fixed delay can be used to wait for these operations to complete, however, to optimize the system's byte programming and erasure operation time, and determine whether internal operations are completed or not, sst39sf040 provides two status bits for detection, that is, the jump displacement dq6 and the Data Query bit dq7. When the chip performs internal operations, you only need to query dq6 or dq7 according to the process shown in figure 3, and then make a timely judgment.

Interface Design of 2 sst39sf040 and MCS-51

2.1 Hardware Design

Hardware design is to build a suitable interface circuit, sst39sf040 connected to the MCS-51 system bus. According to the structure characteristics of sst39sf040 and MCS-51 series single chip microcomputer, we found that the sst39sf040 data line and the reading and writing signal line can be easily connected to the total line of the MCS-51 system, therefore, the main problem to consider is the connection of the sst39sf040 address line. Since its capacity has exceeded the addressing range of the MCS-51, 19 address lines cannot be fully connected to the MCS-51's address bus, so further memory expansion must be performed in the system. Memory expansion can usually be achieved using the idle I/O port Line of the microcontroller as the page address output pin. However, in many application systems, the I/O Ports of single-chip microcomputer are very tight. When there are no redundant I/O Ports, the page address must be provided from the Data Bus output and stored in the latches for backup. The specific method is to directly mount the latches on the Data Bus and arrange an I/o address for them to form a page register. when accessing the memory, write the page address as the data to the page register in advance.

According to the above analysis, the interface circuit between sst39sf040 and MCS-51 can be designed, 4 shows. In this system, 512 KB of memory is divided into 32 pages, each page size is 16 kb. As a result, the page address must be 5 bits and the offset must be 14 bits. The page address is provided before access to the storage. The specific method is to use the "movx" command to output the page address to the 74LS374 lock, then 74LS374 keeps the page address on the address pin A14 ~ of the memory ~ A18. The offset in the page is provided directly in the read/write command of the memory. When the command is executed, the 8-bit lower address a0 ~ A7 is maintained from P0 port output to 74LS373; address A8 ~ A13 is based on the MCU p2.0 ~ P2.5 is provided directly. The above time-based output address and email number a0 ~ A18 takes effect after the read/write control signal starts to work, to achieve access to the sst39sf040 512kb full address space. P2.6 and p2.7 are used as the chip selection signals for skt39sf040 and 74LS374 respectively, and sst39sf040's chip selection signal ranges from 8000h ~ The address range of the chip selection signal of bfffh and 74LS374 is 4000h ~ 7 fffh.

2.2 Software Design

The software design is to write the sst39sf040 operating program, including byte reading, sector or whole part erasure, and byte programming. The following describes the erasure program for 1st sectors. delay25 is a 25 ms delay subroutine. For other operating procedures, see.

The difficulty in programming is how to break down the unit addresses to be accessed in sst39sf040 and map them to the read/write commands. Take the 1st command for the sector erasure operation as an example. The function of this command is to write data aah to the address 55h. For address 5555 H, the maximum value is 5 bits A18 ~ The value of A14 is 01 h, and the value of A13 is 14 bits ~ A0 is 1555 H. The page number determined by the maximum five-bit address must first be written to 74LS374 as the data, and then the data AAH is written to the single dollar determined by the low 14-bit address on the page. When the page number is written, the address in the command can be in H ~ Select one of the 7fffh ranges, that is, the 74LS374 lock is selected. When the writer data is aah, the address in the command can be obtained by adding 8000h to the 1555h address of the 14-bit low location, and the value is 9555 H.

The code for the 1st sector erasure program is as follows:

Knot

This paper analyzes and discusses the interface technology between large-capacity nor flash memory and 8-Bit Single Chip Microcomputer from two aspects of hardware and software, and provides a specific design scheme. Its ideas and methods have a high reference value for the application design of embedded systems. I have applied them to the design and development of a attendance machine product.