Marvell memory Analysis

Config_mv_internal_regs_selective_mapping = y

Select ing internal registers (dispersed, 64 K each), otherwise ing 1 m register space

Sysmap. c file

# If defined (config_mv_internal_regs_selective_mapping)

/* Need to make sure it is big enough to hold all mapping entries */
# Define mem_table_max_entries 30

/* Default mapped entries */
# Define mem_table_entries 7

/* Number of entries to map */
Volatile u32 entries = mem_table_entries;

Struct _ mv_internal_regs_map {
Mv_unit_id ID;
U32 index;
U32 offset;
U32 size;
};

/* Internal registers mapping table */
Struct _ mv_internal_regs_map [] = {
{Dram_unit_id, 0, dram_base, sz_64k },
{Cesa_unit_id, 0, mv_cesa_tdma_reg_base, sz_64k },
{Usb_unit_id, 0, usb_reg_base (0), sz_64k },
{Xor_unit_id, 0, mv_xor_reg_base, sz_64k },
{Eth_gig_unit_id, 0, mv_eth_reg_base (0), sz_8k},/* GBE port0 REGISTERS */
{Eth_gig_unit_id, 1, mv_eth_reg_base (1), sz_8k},/* GBE port1 REGISTERS */
{Sata_unit_id, 0, (sata_reg_base + 0x2000), sz_8k},/* SATA port0 REGISTERS */
{Sata_unit_id, 1, (sata_reg_base + 0X4000), sz_8k},/* SATA port1 REGISTERS */
{Sdio_unit_id, 0, mv_sdio_reg_base, sz_64k },
{Audio_unit_id, 0, audio_reg_base (0), sz_64k },
{Ts_unit_id, 0, tsu_global_reg_base, sz_16k },
{Tdm_unit_id, 0, tdm_reg_base, sz_64k}
};

/* AHB to mbus mapping entry */
Struct map_desc ahb_to_mbus_map [] = {
{(Inter_regs_base + max_ahb_to_mbus_reg_base), _ phys_to_pfn (inter_regs_base + max_ahb_to_mbus_reg_base ),
Sz_64k, mt_device },
};

/* Warning: update of this table requires updating mem_table_entries */
Struct map_desc mem_table [mem_table_max_entries] = {
{(Inter_regs_base + Mpp_reg_base ), _ Phys_to_pfn (inter_regs_base + mpp_reg_base), sz_64k, mt_device },
{(Inter_regs_base + sata_reg_base), _ phys_to_pfn (inter_regs_base + sata_reg_base), sz_8k, mt_device },
{(Inter_regs_base + pex_if_base (0) ,__ phys_to_pfn (inter_regs_base + pex_if_base (0), sz_64k, mt_device },
{Pex0_io_base, _ phys_to_pfn (pex0_io_base), pex0_io_size, mt_device },
{Nflash_cs_base, _ phys_to_pfn (nflash_cs_base), nflash_cs_size, mt_device },
{Spi_cs_base, _ phys_to_pfn (spi_cs_base), spi_cs_size, mt_device },
{Crypt_eng_base, _ phys_to_pfn (crypt_eng_base), crypt_eng_size, mt_device },
};

# Else
Struct map_desc mem_table [] = {
/* No use for pex mem remap */
/* {Pex0_mem_base, _ phys_to_pfn (pex0_mem_base), pex0_mem_size, mt_device },*/
{Inter_regs_base, _ phys_to_pfn (inter_regs_base), sz_1m, mt_device },
{Pex0_io_base, _ phys_to_pfn (pex0_io_base), pex0_io_size, mt_device },
{Nflash_cs_base, _ phys_to_pfn (nflash_cs_base), nflash_cs_size, mt_device },
{Spi_cs_base, _ phys_to_pfn (spi_cs_base), spi_cs_size, mt_device },
{Crypt_eng_base, _ phys_to_pfn (crypt_eng_base), crypt_eng_size, mt_device },
};
# Endif/* config_mv_internal_regs_selective_mapping */

 

Mvcontrolenvspec. h

# DefineMpp_reg_baseZero X 10000

Mbus-L to mbus bridge register (for management of windowx ing)

# Define max_ahb_to_mbus_reg_base 0x20000

 

Mvsyshwconfig. h

/* Internal registers: size is defined in controllerenvironment */
# Define inter_regs_base 0xf000000

 

# Define spi_cs_base 0xf4000000

 

Addresses in map_desc are mapped through MMU. C.