MCS-51 Series Special function registers (excerpt)

1. P0 (80H)

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

2. SP stack pointer (81H)

3. DPTR data pointer (made up of DPH and DPL)

DPL data pointer low eight bit (82H)

DPH data pointer eight bits high (83H)

4. PCON Power Management Register (87H)

Smod

——

——

——

GF1

GF0

Pd

Idl

Smod: Baud rate multiplier bit. Smod=0, constant when smod=1, multiply.

GF1,GF0: Universal flag bit.

PD: Power-down mode bit. When pd=1, enter the power-down mode.

IDL: Standby mode bit. When idl=1, enter Standby mode.

5. Tmod Timer/Count register (89H)

GATE

c/t

M1

M0

GATE

c/t

M1

M0

Gate: Gate-control. When gate=0, the timer is started directly by TR, and when gate=1, the external int is 1 o'clock, and TR starts the timer.

C/T: function Selection bit. C/t=0 when the timer is c/t=1, it is the counter.

M1,M0: Mode select bit.

M1	M0	Working style	Way description
0	0	Mode 0	13-bit counter
0	1	Mode 1	16-bit counter
1	0	Mode 2	8-bit automatic reload counter
1	1	Mode 3	T0: Divided into two 8-bit counters, T1: Stop count.

6. TCON Timer/Count control register (88H)

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

TF1: Timer 1 overflow flag. By hardware 1, and enter the interrupt, after entering the interrupt service program, by the hardware clear 0, the query method by the software clear 0.

TR1: Timer run control bit. Tr1=0, when T1;tr1=1 is turned off, the T1 is started.

TF0: Timer 0 overflow flag. By hardware 1, and enter the interrupt, after entering the interrupt service program, by the hardware clear 0, the query method by the software clear 0.

TR0: Timer run control bit. Tr0=0, when T0;tr0=1 is turned off, the T0 is started.

IE1: External interrupt 1 request flag.

IT1: External Interrupt 1 trigger mode. When the it1=0 is low-level trigger mode, it1=1 is the negative jump trigger mode (Edge trigger).

IE0: External interrupt 0 request flag.

IT0: External interrupt 0 trigger mode. When the it0=0 is low-level trigger mode, it0=1 is the negative jump trigger mode (Edge trigger).

7. P1 (90H)

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

8. SCON Serial Control Register (98H)

SM0

SM1

SM2

REN

TB8

RB8

TI

RI

SM0,SM1: Serial mode control.

SM1	SM0	Working style	Function description	Baud rate
0	0	Mode 0	8-bit Synchronous shift register	Fosc/12
0	1	Mode 1	10-bit UART	Variable
1	0	Mode 2	11-bit UART	FOSC/64 or FOSC/32
1	1	Mode 3	11-bit UART	Variable

SM2: Multi-machine communication control bit. Sm2=0, multi-machine communication is forbidden when sm2=1, and multi-machine communication is allowed.

REN: Allows serial receive bits. Serial reception is not allowed when ren=0, and serial receive is permitted when ren=1.

TB8: Send data Nineth bit (D8).

RB8: Receive data nineth bit (D8).

TI: Send interrupt flag bit.

RI: Receive interrupt flag bit.

9. P2 (a0h)

P2.7

P2.6

P2.5

P2.4

P2.3

P2.2

P2.1

P2.0

10. IE Interrupt Allow control Register (a8h)

Ea

——

ET2

Es

ET1

EX1

ET0

EX0

EA:CPU interrupts the total allowable bit. Ea=0, all interrupt requests are masked, and the CPU is open when ea=1 is interrupted.

ES: Serial port interrupt allowed bit. Es=0, the serial port is not interrupted and the serial port is allowed to interrupt when Es=1.

ET1:T1 interrupt allow bit. When Et1=0, T1 is forbidden, and T1 is allowed to interrupt when et1=1.

EX1: External interrupt 1 (INT1) allow bit. When Ex1=0, INT1 is forbidden, and INT1 is allowed to interrupt when ex1=1.

Et0:t0 interrupt allow bit. When Et0=0, T0 is forbidden, and T0 is allowed to interrupt when et0=1.

EX0: External interrupt 0 (INT0) allow bit. When Ex0=0, INT0 is forbidden, and INT0 is allowed to interrupt when ex0=1.

Et2:t2 interrupt allow bit. When Et2=0, T2 is forbidden, and T2 is allowed to interrupt when et2=1.

11. P3 (b0h)

P3.7

P3.6

P3.5

P3.4

P3.3

P3.2

P3.1

P3.0

12. IP Interrupt Priority Control Register (B8H)

——

——

PT2

Ps

PT1

PX1

PT0

PX0

PS: Serial port interrupt priority control bit. Ps=0, the priority level is low, and when Ps=1, the serial port is set to high priority interrupt.

PT1:T1 interrupt priority control bit. When pt1=0, the priority is low, and when Pt1=1 is set, the T1 is a high-priority interrupt.

PX1: External interrupt 1 (INT1) priority control bit. When px1=0, the priority level is low; When px1=1, setting an external interrupt 1 (INT1) is a high-priority interrupt.

Pt0:t0 interrupt priority control bit. When pt0=0, the priority is low, and when Pt0=1 is set, the T0 is a high-priority interrupt.

PX0: External interrupt 0 (INT0) priority control bit. When px0=0, the priority level is low; When px0=1, setting an external interrupt 0 (INT0) is a high-priority interrupt.

13. PSW Program Status Word register (d0h)

CY

AC

F0

RS1

RS0

OV

F1

P

CY: Carry flag.

AC: Semi-carry flag.

F0,F1: User flag bit.

RS1,RS0:

RS1	RS0	Register Group	In-Chip RAM address
0	0	Group No. 0	00h~07h
0	1	Group 1th	08h~0fh
1	0	Group 2nd	10h~17h
1	1	Group 3rd	18h~1fh

OV: Overflow flag.

P: base-even flag.

14. ACC Accumulator A. (e0h)

15. b b Register (F0H)

MCS-51 Series Special function registers (excerpt)