MCU new knot

I have been using a single-chip microcomputer for a while, but I am also familiar with the use of some modules. I am not very familiar with the working principle of the single-chip microcomputer.

Therefore, it is difficult to study in depth at last. At best, we are familiar with the programming of C51. To understand the working principle of a MCU, it is necessary to understand assembly.

In the programming process, the most important thing is timing! Whether it is reading/writing memory or communication, only time series matching can be written.

Efficient code with few bugs. These are just the things that need to be mastered. So I learned MCS51 again and got some new understandings.

 

Command attributes: Command length and execution time.

The instruction length is the ROM space stored in the Rom. After the compiler assembles the program, the size of the program is given. This value is the storage space.

The Rom space occupied by this program (of course, it is stored in binary format ). The register closely related to Rom is PC,

The PC is used to point to the ROM address. Although it is used to direct to the next instruction, its value does not always add a Forward Command,

The increment of PC is related to the instruction length. First, let's take a look at the 3-byte command mov 30 h, #20 h stored in Rom.

Obviously, this command occupies 3 bytes of space, and the PC + 3 is used to execute the next command.

Note that the minimum instruction cycle is equal to a machine cycle, rather than a clock cycle. The NOP instruction execution time in a single cycle is a machine cycle.

Of course, the cycle of each instruction is fixed. The read command operation is related to the ale signal. Only one read command operation is executed when the ale is valid.

When the ALE (address locked enable) signal is not used to store external Ram addresses, its cycle is the 6-division of the oscillating clock.

(If it is a single-instruction dual-cycle instruction, the four value-taking operations are only valid for the first time)

 

Register (pointer) SP, DPTR, and PC

The role of the PC is the ROM address counter.

SP always points to the top of the stack (it should be a stack, and the stack and stack are two different concepts of RAM), while the stack is in the internal RAM, so SP is the RAM address counter.

DPTR can point to external RAM (write operation), or ROM (query table command ).

 

It is not difficult to write single-module code. The difficulty is that multiple modules can be combined to work collaboratively without being a module.

In fact, as a single-chip microcomputer control system, writing code requires the design of the program framework at the operating system level, that is, the Program Framework for streaking.

In addition, latency programs are often used. However, it is difficult to implement precise latency in C code, because the disassembly code of the compiler will always be different for different delayed code writing methods.

At this time, it is necessary to sacrifice the timer or embed the Assembly to achieve precise latency. But for those who do not understand compilation and do not want to sacrifice resources,

Or you can use the C51 to write the code that approaches the exact latency.