Memory and CPU bandwidth calculation

 

CPU bandwidth refers to the data transmission rate between the CPU and the North Bridge. From the calculation method of the CPU frontend bus bandwidth, "frontend bus bandwidth = system external frequency × n times speed × 64-bit bus bit width/8, we can know that the transmission bandwidth of the P4 series 133mhz external frequency, that is, the CPU speed of the front-end bus is 533 MHz (133mhz external frequency × 4 times speed), up to 4.2 Gb/s (533mhz × 8. Therefore, we can calculate the CPU bandwidth of other front-end Bus: the transmission bandwidth of 266 MHz FSB is 2.1 Gb/s, and that of 333 MHz FSB is 2.7 Gb/s; the transmission bandwidth of 400 MHz FSB is 3.2 Gb/s, the transmission bandwidth of 533 MHz FSB is 4.2 Gb/s, and the transmission bandwidth of 800 MHz FSB is 6.4 Gb/s. Memory rate refers to the memory operating frequency. For example, the ddr266 operating frequency is 266 MHz. According to the memory bandwidth algorithm: bandwidth = bus bit width/8 × number of packets exchanged in a clock period × bus frequency, ddr266 bandwidth = 64/8 × 2 × 133 = 2128, and its transmission bandwidth is 2.1 Gb/s, therefore, ddr266 is also known as pc2100, where 2100 refers to its memory bandwidth of about 2100 MB. Similarly, ddr333 operates at 333 MHz, and the transmission bandwidth is 2.7 Gb/s, commonly known as pc2700. ddr400 operates at 400 MHz, and the transmission bandwidth is 3.2 Gb/s, commonly known as pc3200. [/ Memory bandwidth calculation formula: bandwidth = memory clock frequency × memory bus bits × multiplication coefficient/8. Taking the current ddr400 memory as an example, the operating frequency is 200 MHz, and the number of bits in the Data Bus is 64bit. because both the rising and falling edges transmit data, the doubling factor is 2, and the bandwidth is: 200 × 64 × 2/8 = 3.2 Gb/s (if it is a dual-channel consisting of two memories, the bandwidth is 6.4 Gb/s ). Obviously, at the current technical level, the operation frequency is difficult to multiply. At this time, the number of data bus digits and the doubling coefficient are the technical breakthrough point. Calculating the total bandwidth of memory bandwidth may be one of the important criteria that determine the performance of a group of memory. What does this mean? In fact, it is not difficult to really understand, and it is also very easy to calculate. The total memory bandwidth we just mentioned is actually the maximum data capacity that can be transferred within one second in an ideal situation. The formula is also very simple: total memory bandwidth (Mbytes) = maximum clock speed (MHz) x bus width (BITs) X number of data segments per clock/8. Let's explain it. It is best to understand the number of data segments per clock-You just need to remember that if your memory is SDR, the value here is equal to 1, if you are using DDR or RDRAM, the value is 2. Then we divide this value by 8, which means converting the bit unit into bytes. Therefore, for the standard pc2100 DDR memory, its maximum clock frequency should be 133 MHz, and its memory bus width should be 64 bit, with each clock data segment being 2. So (133x64X2)/8 = 2128 Mb/s. 2128 MB can be transferred in one second. Now you know why pc2100? Here is another example. Take pc800 RDRAM for calculation this time. The maximum clock frequency is 400 MHz, the memory bus width is 16 bits, and each clock data segment is 2, then the formula is (400x16x2)/8 = 1600 Mb/s. As you can see, the pc2100 DDR memory can provide up to 2.1 Gb/s of bandwidth, while the RDRAM memory bandwidth can only reach 1.6 Gb/s, since RDRAM was previously used, the two memories can provide a total of 3.2 Gbit/s of memory bandwidth, while the new generation of Rimm memory (the bus is a 32-bit RDRAM memory) two data channels will be used for work, so their bandwidth is doubled a few times-so it becomes 3.2 Gb/s and can be used with a separate memory. Memory bandwidth calculation formula Liu Ting's computer: 13: 13 2002-5-12 memory bandwidth = memory operating frequency X memory bus width/8 (bandwidth time and byte conversion) both the SDR and DDR are 64-bit bus widths, but the DDR can transmit data at both the rising and falling edges of the clock signal. Therefore, the calculated bandwidth is X2. RDR has a narrow bus bandwidth of only 16 bits, but RDR uses symmetric Transmission Mode during operation. Therefore, the calculated bandwidth is X2. Ddr266 and 333 are named because the theoretical efficiency of the DDR is twice that of the SDR. In order to distinguish between the SDR, the working frequency of the SDR is twice the same, DDR mapped to 133 MHz and MHz respectively. The naming method for pc1600, 2100, and 2700 refers to the actual bandwidth of the DDR, which is mapped to the DDR at 100, 133, and 166mhz respectively. The CPU and memory bottlenecks are generated because the current memory speed is much lower than the processor speed. The external frequency is not necessarily the operating frequency of the CPU's BIU (Bus Interface Unit. The current speed of the bus is generally 500 MHz to MHz. Like the CPU, the bus frequency is also obtained by doubling. The memory asynchronous working mode provided by the current motherboard is that the memory frequency is less than the bus frequency. For example, the bus runs at 266mhz and the memory runs at 100mhz. You should say 266 is the DDR memory, 266mhz DDR, clock or 133 MHz. If your duron is a 200 MHz external frequency, that is to say, the bus frequency is 100 MHz, then your DDR operation clock is also MHz. Http://www.liuting.net/hardware/knowledge/memoryband.htm Intel series, the CPU is connected to beiqiao chip through FSB, and beiqiao chip is responsible for communicating with memory and video card! The FSB of Intel Pentium 4 is 400, 533, 800 MHz, and the bus bandwidth is 3.2 GB/sec, 4.2 GB/sec, and 6.4 GB/sec, respectively, the memory bandwidth provided by DDR 266/DDR 333/DDR 400 is 2.1 GB/sec, 2.7 GB/sec, and 3.2 GB/sec. Data bandwidth = (bus frequency × data Bit Width) Listen 8. Whether Single-core, dual-core, or multi-core CPUs, the bandwidth of the front-end bus is calculated in the same way as that of single-core CPUs. The reason is simple. There is only one front-end bus for these multi-core CPUs and can only be connected to a single memory controller. Here we will talk about the SMP platform. On a multi-processor platform (except for a desktop PC), no CPU has its own independent memory controller and corresponding memory module. All CPUs work in parallel. The 64-bit CPU only improves the physical memory addressing space of the CPU, and does not affect the bandwidth of the CPU frontend bus. Therefore, the calculation method is the same as that of the former.