Mii Interface Introduction

1. Introduction

MII (Media independent Interface) or media independent interface, it is the Ethernet industry standard defined by IEEE-802.3. It includes a data interface and a management interface between Mac and PHY. Media independence indicates that any type of PHY device can work correctly without the MAC hardware being redesigned or replaced. There are many types of Mii interfaces, commonly used are Mii, RMII, Smii, Ssmii, Sssmii, GMII, RGMII, SGMII, which are described below.

2. Introduction of MII interface

There are 16 wires in the Mii interface.
RXD (Receive data) [3:0]: Data received signal, a total of 4 signal lines;
Tx_er (transmit error): Send data error signal, synchronized to TX_CLK, high active, indicating that the data transmitted during the Tx_er validity period is invalid. For 10Mbps rate, tx_er does not work;
Rx_er (receive error): Receive data error signal, synchronous to RX_CLK, high active, indicating that the data transmitted during the Rx_er validity period is invalid. For 10Mbps rate, rx_er does not work;
Tx_en (transmit enable): Sends the Enable signal, only in the tx_en validity period incoming the data to be valid;
RX_DV (reveive data Valid): Receives the data valid signal, the function type is in the transmission channel tx_en;
TX_CLK: Send reference clock at 100Mbps, clock frequency at 25mhz,10mbps rate, clock frequency is 2.5MHz. Note that the direction of the TX_CLK clock is directed from the PHY side to the Mac side, so this clock is provided by PHY.
RX_CLK: Receives the data reference clock at 100Mbps, at a clock rate of 25mhz,10mbps, and a clock frequency of 2.5MHz. The RX_CLK is also provided by the PHY side.
Crs:carrier sense, carrier detection signal, do not need to synchronize with the reference clock, as long as there is data transmission, CRS is effective, in addition, CRS only PHY in half-duplex mode valid;
Col:collision DETECTD, collision detection signal, does not need to be synchronized to the reference clock, only PHY in half-duplex mode is valid.

3, Rmii interface Introduction

Rmii, reduced Mii, is a simplified board for Mii, which reduces the number of connections from Mii to 8 by 16.
TXD[1:0]: Data transmission signal line, the data bit width is 2, is half of the Mii interface;
RXD[1:0]: Data receive signal line, data bit width is 2, is half of the Mii interface;
Tx_en (transmit enable): Data transmit enable signal, same as the function of this signal line in the Mii interface;
Rx_er (receive error): The data receives the error signal, the same as the function of the signal line in the Mii interface;
Clk_ref: is a 50MHz reference clock provided by an external clock source, and unlike the Mii interface, the receive clock and transmit clock in the Mii interface are separate and are provided by the PHY chip to the MAC chip. It is important to note that since the data receive clock is provided by the external crystal instead of the carrier signal, the data receiving part in the PHY layer chip needs to design a FIFO that coordinates two different clocks and provides buffering when sending the received data. The transmission portion of the PHY layer chip does not require a FIFO, it sends the received data directly to the Mac.
CRS_DV: This signal is formed by merging the RX_DV and CRS two signals from the Mii interface. When the media is not idle, CRS_DV and RE_CLK are given in a different way. When CRS is over RX_DV (i.e. the carrier disappears and there is data to be transmitted in the queue), the CRS_DV is switched back and forth between 0 and 1 at the 25mhz/2.5mhz frequency of the half-tuple boundary. As a result, the Mac is able to accurately recover RX_DV and CRS from CRS_DV.
At 100Mbps rates, TX/RX samples one data per clock cycle, and at 10Mbps rates, tx/rx samples one data every 10 cycles, so tx/rx data needs to be retained 10 cycles on the data line, which is equivalent to 10 times the data is sent.
When the PHY layer chip receives a valid carrier signal, the CRS_DV signal becomes valid, if there is no data in the FIFO, then it sends out all 0 of the data to the Mac, then when the FIFO is filled with valid data frame, the data frame begins with "101010-" the intersection of the preamble, when the data appears " 01 "Of the bit, on behalf of the formal data transfer begins, the MAC chip detects this change, thereby starting to receive data.
When the external carrier signal disappears, the CRS_DV becomes invalid, but if there is data to be sent in the FIFO, the CRS_DV will become valid in the next cycle, and then invalid until the data in the FIFO is sent out. If an invalid carrier signal or invalid data encoding occurs during the receive process, the rx_er becomes valid, indicating that the physical layer chip receives an error.

4, Smii interface Introduction

Smii is serial mii, serial mii meaning, compared with rmii, the connection is further reduced to 4 root.
TXD: Sends the data signal, the bit width is 1;
RXD: Receives the data signal, the bit width is 1;
Sync: Send and receive data synchronization signal, 1 times per 10 clock cycle high, indicating synchronization.
Clk_ref: A reference clock shared by all ports, 125MHz in frequency, why 100Mbps rate with 125MHz clock? Since 2-bit control signals are inserted in every 8 bits of data, see below.
Txd/rxd is a group of 10 bits, with sync high to indicate the beginning of a set of data, 10 clock cycles after sync is high, the data on TXD is: txd[7:0], tx_en, tx_er, the meaning of the control signal is the same as in the Mii interface The data output on RXD is: rxd[7:0], RX_DV, crs,rxd[7:0] are related to RX_DV, when RX_DV is active (High level), rxd[7:0] is transmitted by the physical layer received data. When the RX_DV is invalid (low level), the rxd[7:0] is transmitted on the physical layer's state information data. See table below:

At a rate of 10Mbps, each group of data is repeated 10 times, and the Mac/phy chip is sampled every 10 cycles. The Mac/phy chip will be serial/and converted after receiving the data.

5, Ssmii Interface Introduction

Ssmii is serial sync MII, called serial synchronization interface, similar to the Smii interface, just send and receive the use of independent reference clock and synchronous clock, no longer like the smii to send and receive a common reference clock and synchronous clock, transmission distance is farther than smii.

6, Sssmii Interface Introduction

The sssmii is the source sync Serial Mii, called the origin synchronous serial Mii interface, the difference between the sssmii and the ssmii is the direction of the reference clock and the synchronous clock, ssmii the TX/RX reference clock and the synchronous clock are provided by the PHY chip, The Sssmii TX reference clock and synchronous clock are provided by the MAC chip, the RX reference clock and the synchronous clock are provided by the PHY chip, so the name is called the source synchronous serial.

7, Gmii Interface Introduction

Compared to the Mii interface, the data width of the gmii is changed from 4 bits to 8 bits, and the control signals in the Gmii interface such as Tx_er, Tx_en, Rx_er, RX_DV, CRS, and Col function as in the Mii interface, sending the reference clock GTX_CLK and receiving the reference clock Rx_ The CLK frequency is 125MHz (1000mbps/8=125mhz).
Here is a point to note, that is to send a reference clock GTX_CLK, which is different from the Mii interface TX_CLK, the Mii interface TX_CLK is provided by the PHY chip to the MAC chip, and Gmii interface gtx_ CLK is provided to the PHY chip by a Mac chip. The two directions are different.
In practice, the vast majority of gmii interfaces are compatible with the Mii interface, so the general Gmii interface has two send reference clocks: TX_CLK and GTX_CLK (the direction of the two is not the same, previously said), when used as Mii mode, use Tx_ 4 in CLK and 8 data lines.

8, Rgmii Interface Introduction

Rgmii, reduced GMII, is a simplified version of rgmii, reducing the number of interface signal lines from 24 to 14 (Col/crs port status indication signal, not drawn here), the clock frequency is still 125mhz,tx/rx data width from 8 to 4 bits, To keep the transmission rate of 1000Mbps constant, the Rgmii interface samples data on both the rising and falling edges of the clock. On the rising edge of the reference clock, send the txd[3:0]/rxd[3:0] in the Gmii interface, sending txd[7:4]/rxd[7:4 in the Gmii interface on the falling edge of the reference clock]. The RGMI is also compatible with 100Mbps and 10Mbps two rates, at which point the reference clock rate is 25MHz and 2.5MHz respectively.
Tx_en Signal Line transmits tx_en and tx_er two kinds of information, sends tx_en along the rising edge of the TX_CLK, sends tx_er along the descending edge; Likewise, RX_DV and RX_DV Two kinds of information are also transmitted on the rx_er signal line, sending RX_CLK on the rising edge of RX_DV, The falling edge sends Rx_er.
　　

Mii Interface Introduction (RPM)