MSI and MSI-X

Msi

The pci2.2 specification introduces MSI as a traditional line-based interrupt solution. Msi allows the device to allow interruption by writing a specific value to a specific address, rather than using a proprietary pin to trigger the interruption. Note that the destination address and data of a message are treated as vectors. Compared with traditional interruptions, MSI provides the following key advantages:

• One PCI function can request up to 32 MSI messages
• They are in-band messages, rather than pins, and select the target address on the host bridge.
• They can send data together with interrupted messages, and the data load is variable.
• They are not shared, so the MSI assigned to a device can be considered unique in the system.

MSI-X

Pci3.0 defines an extension form of MSI, known as MSI-X, which addresses the limitations of MSI. For example, numa-based servers that support a large number of CPUs are deployed in large quantities. Currently, it is not appropriate for each adapter in MSI to support only 32 MSI messages. The MSI-X addresses this limit by increasing the number of messages to 2048. Another example is that MSI only provides one MSI address. The target of all messages is the same CPU group. The MSI-X overcomes this problem by providing a unique address and value pair for each message. The core changes in pci3.0 for MSI-X are as follows:

• 2048 messages instead of 32 messages are supported.
• Provides an independent Message Address and data for each message.
• Support per vector mask

MSI and MSI-X