Msi cache consistency Protocol

Based on the write policy of the cache, there are two types of cache: Direct Write and write back WB:

1. Write directly to the cache: Once a word in the cache is modified, it must be modified immediately in the primary storage.

2. write back to the cache: it is not immediately written back, but when the modified words are replaced or cleared from the cache, the primary storage is actually modified.

In the design of the listener protocol, there are two main designs: one is to write directly to the cache, the other is to write back to the cache, the other is to write invalid WI, or write update Wu Protocol

Msi Protocol

Invalid MSI (modified, shared, invalid)

Status

1. Invalid I status:

2. Shared s status: This indicates that the block has not been modified in the cache and is the latest in the primary memory. It may or may not have been copied in other caches.

3. Modify the M status: it means that only the latest copy of the block in the cache is available, the copy in the primary memory is outdated, and there is no valid copy of the block in other caches.

Event:

In the cache consistency Protocol, each cache controller receives two inputs:

1. Requests sent by the processor: The processor reads prwr from the prrd Processor

2. Transactions intercepted on the Bus: Bus reads busrd, bus mutex reads busrdx, and bus writes back buswb

Bus read busrd: the high-speed cache controller places the address on the bus and requests a data block, which is provided by the primary storage or cache.

Bus mutex-read: request data block. The purpose is to modify the data block and exclusive to itself. Other caches are invalid.

Bus write back buswb: cache writes data blocks to memory

To support the above events, the high-speed cache Controller provides a new event: flush, in order to respond to the transactions that appear on the bus, in addition, the block requested by the firm can be directly cached from the cache to the bus, instead of being passed into the data through the memory.

A/B indicates that the cache controller has observed that event a has occurred, or that event a has led to the conversion. In addition to status conversion, Action B is also generated; "-" indicates an empty action, and the flush action indicates that the cache requests the block to the bus.

Invalid status:

1. when a processor reads a prrd event, a cache miss occurs, and new data is loaded. However, other caches may or may not exist, so the data enters the S state, of course, the support for bus read events is required, so the bus read event busrd is triggered.

2. when a processor writes a prwr event, it will cause a cache miss and call the bus to mutex read busrdx event (the purpose is to tell other caches that I want to modify this cache, and you will not delete it first ), load the data to be written into the cache (this is because the direct write and no allocation policy is used), and then modify the data to enter the M status.

Sharing status:

1. When a processor reads a prrd event, it directly hits or is in the S state because the data is in the current cache and is the latest.

2. when a processor writes a prwr event, it calls the bus mutex read busrdx event (the purpose is to tell other caches that I want to modify this cache, and you will not delete it first). After the data is updated, you need to enter the M status to inform you that this is the latest data, and the data in the primary storage is outdated.

3. When a read busrd event is received on the bus, it is irrelevant to me when the shared State receives the read information from other bus, so it is still in the S state.

4. When I receive an event of mutex-read busrdx on the bus, I know that you want to be the boss, so I can only follow your arrangement to invalidate myself. Entering the I status

Modified status

1. When a processor reads a prrd event, because it is a read event, and M indicates that the data in the current cache is newer than others, it is hit directly without affecting other caches. So it enters the M status.

2. When a processor writes a prwr event, it is also because the current cache is the latest, so direct update and writing does not affect other caches, so it still enters the M state.

3. when I receive a read busrd event on the bus, because I am in the M status, my data is up-to-date, so of course I provide the data, so a flush event is generated, finally, it enters the S state.

4. when you receive an event on the bus that has mutex read busrdx, because you told me that you can only be the boss, but I can only give it out, but before giving it out, I need to hand over the Yu xi, so first flush, and then enters the invalid I state to make you the boss.

Msi cache consistency Protocol