MSP430 library DMA Library

Direct Memory Access (dmadirect Memory Access) uses hardware to directly transmit high-speed data between memory and memory or between memory and I \ O devices without CPU intervention. This method is usually used to transmit data blocks. The msp430f16x series single-chip microcomputer contains a DMA module, and almost all internal Peripherals can trigger DMA to start data access. This module is implemented hereProgramCommon function libraries for ease of use.

2. Hardware introduction:

The msp430f15x/16x series single-chip microcomputer has a DMA controller to ensure high-speed data transmission. For example, the DMA controller can directly transfer the content of the ADC conversion memory to the ram unit.

The extended DMA of MSP430 Series Single-Chip Microcomputer has all the peripherals trigger. It can provide advanced and configurable data transmission capabilities without CPU intervention, thus accelerating the MCU-based signal processing process, the DMA transmission trigger source is completely transparent to the CPU. The DMA controller can precisely control the transmission between memory and external hardware. DMA eliminates the data transmission delay time and various overhead, which frees 16 of the CPU to use more time for data processing, rather than executing ongoing tasks.

The DMA module of the msp430f16x series single-chip microcomputer has the following features: data transmission requires no CPU intervention and is completely managed by the DMA controller. Data can be transmitted in Block Mode up to 65536 bytes within the entire address space range. This improves the data throughput of on-chip peripherals and achieves high-speed transmission, only two mclks are required for the transmission of each word or byte. This reduces system power consumption. The CPU can be in ultra-low power mode even when the on-chip peripherals input or output data; the transmission of byte and word data can be mixed: DMA transmission can be byte to byte, word to word, byte to word or word to byte. When a word is transferred to a byte, only the lower bytes in the word can be transmitted. when the data is transferred from a byte to a lower byte, the high byte is automatically cleared; four transmission addressing modes: fixed address to fixed address, fixed address to block address, block address to fixed address and block address to block address; flexible triggering mode: edge or Level Trigger. Single, block, or burst Block Transmission Mode: each time a DMA Operation is triggered, data of different scales can be transmitted as needed

Shows the four addressing modes of DMA:

DMA controller module: three independent transmission channels: Channel 0, Channel 1, and Channel 2. Each channel has its own source address register, Destination Address Register, Transfer Data Length register, and control register. Requests triggered by each channel can be allowed and disabled separately. configurable channel priority: Priority ruling module. The transmission channel priority can be adjusted to determine the priority of the channel that triggers the request at the same time, determine which channel has the highest priority. The DMA controller of MSP430 can adopt a fixed priority or a cyclic priority. The program command control module. Before each DMA channel starts transmission, the CPU needs to program related commands and mode control to determine the type of DMA channel transmission. configurable transfer trigger: trigger source selection module, dmareq (software triggered) timer_accr2 output, timer_bccr2 output, I2C data receiving preparation, I2C data sending preparation, usart receiving and sending data, dac12ifg of dac12 module, adc12ifgx of adc12 module, dmaxifg, and dmae0 External Trigger source. It also has the ability to expand the trigger source.

There are six DMA transmission modes: single-byte or single-byte transmission; block transmission; burst transmission; repeated single-byte or single-byte transmission; repeated block transmission; repeated burst transmission. In the first three cases, the dmaen is automatically reset after the transmission is complete. During the next transmission, you need to reset the dmaen bit to enable the DMA channel. The last three are in repeat mode. After one transmission is complete, the dmaen is not reset. When you start again, you can start data transmission again. Six transmission modes are set through the dmadtx register:

Dmadtx Transfer Mode description000 single transfer each transfer requires a trigger. dmaen is automatically cleared when dmaxsz transfers have been made.001 block transfer a complete block is transferred with one trigger. dmaen is automatically cleared at the end of the block transfer.010, 011 burst-block transfer CPU activity is interleaved with a block transfer. dmaen is automatically cleared at the end of the burst-block transfer.100 repeated single transfer each transfer requires a trigger. dmaen remains enabled.101 repeated block transfer a complete block is transferred with one trigger. dmaen remains enabled.110, 111 repeated burst-block CPU activity is interleaved with a block transfer. transfer dmaen remains enabled.

Single-word or single-byte Transmission: The DMA channel is defined as a single-word or single-byte transmission mode. Transmission of each word or byte triggers a signal. If dmadtx is set to 0, the single-byte or single-byte transmission mode is defined. After the specified transmission is completed, the dmaen bit is automatically cleared. If you need to transmit the data again, you must reset the dmaen. If dmadtx = 4 is set to the duplicate single-byte or single-byte transmission mode, the dmaen bit remains set, and the transmission is triggered at a time. The number of units stored in the dmaxsz register. If this register is 0, no data is transmitted. Before the transfer, the value of the dmaxsz register is written to a temporary register. After each operation, dmaxsz performs the subtraction operation. When dmaxsz is reduced to zero, the corresponding temporary register places the original value in dmaxsz and the corresponding dmaifg flag.

Block Transmission Mode: In Block Transmission Mode, one data block can be transferred at a time. Set dmadtx = 1 to block transmission mode. After each data block is transferred, the dmaen bit is automatically cleared. This bit is reset before the next data block is triggered. When a data block is transmitted, other transmission requests are ignored. Set dmadtx = 5 to the duplicate block transmission mode. After a data block is transferred, the dmaen bit remains set. Then, a new trigger can cause another data block transfer. The number of units contained in the data block stored in the dmaxsz register. Dmasrcincr and dmadstincr reflect the change of the destination address and source address during data block transmission. During block transmission or duplicate block transmission, the values of the dmaxsa, dmaxda, and dmaxsz registers are written to the corresponding Temporary registers. The temporary values of the dmaxsa and dmaxda registers are increased or decreased during block transmission, while dmaxsz reduces the count during block transmission, it always reflects the number of units in the current data block that have not been transferred. When dmaxsz is reduced to 0, the corresponding temporary register places the original value into dmaxsz, the corresponding dmaifg is also set. During block transmission, the CPU stops working and does not participate in data transmission. The data block requires 2 × mclk × dmaxsz clock periods. When each data block is transferred, the CPU restarts before the pause.

Burst Block Transmission Mode: This is similar to the block transmission mode, except that every four characters or bytes are transmitted, the DMA releases the internal BUS, And the CPU runs two mclk cycles. During the transmission, the CPU has 20% of the execution time, the block transmission can run only after the DMA transmission is complete.

DMA trigger Source: the trigger source of each channel is controlled by dmaxtselx bits. These bits must be set when the dmaen bits are 0; otherwise, unexpected DMA trigger may occur.

 
Dmaxtselx operation0000 dmareq bit (software trigger) 0001 taccr2 ccifg bit0010 tbccr2 ccifg bit0011 urxifg0 (UART/SPI mode), usart0 data received (I2C mode) 0100 utxifg0 (UART/SPI Mode ), usart0 transmit ready (I2C mode) 0101 Gbit/s bit0110 adc12 Gbit/s bit0111 taccr0 Gbit/s bit1000 tbccr0 ccifg bit1001 Gbit/s bit1010 Gbit/s bit1011 multiplier no action1101 no action1110 Gbit/s triggers DMA Channel 01111 External Trigger dmae0
 

In addition, the interrupt program of the single chip microcomputer does not affect the DMA transmission. During the DMA transmission process, the single chip microcomputer does not respond to the external NMI interrupt (when the DMA control bit ennmi bit is 1, The NMI interrupt is returned, otherwise, all interrupts are not processed. The system interrupt processing program must be run only after the DMA data transmission is completed.

DMA interruption: when the value of the dmaxsz register is reduced to 0 during data transmission, the DMA is set to dmaifg. The DMA interrupt and the dac12 module share the interrupt vector, when using the interrupt, the software must determine the specific interrupt. After the response is interrupted, the dmaifg will not be automatically reset. When using the service, the software must reset the dmaifg bit.

The DMA registers are as follows:

Register short form register type address initial statedma Control 0 dmactl0 read/write 0122 H reset with pordma Control 1 dmactl1 read/write 0124 H reset with pordma channel 0 control dma0ctl read/write 01e0h reset pordma channel 0 source address destination read/write 01e2h unchangeddma channel 0 Destination Address dma0da read/write 01e4h unchangeddma channel 0 transfer size limit read/write 01e6h unchangeddma Channel 1 control dma1ctl read/write 01e8h Reset with pordma Channel 1 source address dma1sa read/write 01eah unchangeddma Channel 1 destination address dma1da read/write 01ech unchangeddma Channel 1 transfer size limit read/write 01eeh unchangeddma Channel 2 control dma2ctl read/write 01f0h reset with pordma Channel 2 source address dma2sa read/write 01f2h unchangeddma Channel 2 Destination Address dma2da read/write 01f4h unchangeddma Channel 2 Transfer size dma2sz read/write 01f6h unchanged

For details about each register, refer to the User Guide provided by TI.

4. Program Implementation:

The use of DMA is mainly the initial settings of the DMA register. After the configuration is complete, the DMA can automatically transmit data after receiving the trigger signal.

The setting function is as follows:

 Void Dmainit ( Char Channel, Char Trigger, Char Transmode, Char Srcmode, Char Dstmode, Unsigned int SRC, Unsigned int DST, Unsigned int Size ){ Unsigned int * Dmaxctl, * dmaxsa, * dmaxda, * dmaxsz; dmactl0 = trigger <(Channel <2); dmactl1 = 0x04; // When the DMA receives the trigger request, wait until the execution of the current command is complete  Switch (Channel) // Select the DMA channel currently set { Case 0: dmaxctl = ( Unsigned int *) & Dma0ctl; dmaxsa = ( Unsigned int *) & Dma0sa; dmaxda = ( Unsigned int *) & Dma0da; dmaxsz = ( Unsigned int *) & Dma0sz; Break ; // Pointer = 0-channel control  Case 1: dmaxctl = ( Unsigned int *) & Dma1ctl; dmaxsa = ( Unsigned int *) & Dma1sa; dmaxda = ( Unsigned int *) & Dma1da; dmaxsz = ( Unsigned int *) & Dma1sz; Break ; // Pointer = 1-channel control  Case 2: dmaxctl = ( Unsigned int *) & Dma2ctl; dmaxsa = ( Unsigned int *) & Dma2sa; dmaxda = ( Unsigned int *) & Dma2da; dmaxsz = ( Unsigned int *) & Dma2sz; Break ; // Pointer = 2-channel control } Switch (Transmode) // Set the transmission mode of the DMA Channel { Case  'S' : * Dmaxctl = dmadt_0; Break ;// Single transmission  Case  'S' : * Dmaxctl = dmadt_4; Break ; // Repeat a single transmission  Case  'B' : * Dmaxctl = dmadt_1; Break ; // Block Transmission  Case  'B' : * Dmaxctl = dmadt_5; Break ; // Duplicate transfer  Case 'I' : * Dmaxctl = dmadt_2; Break ; // Burst Block Transmission staggered  Case  'I' : * Dmaxctl = dmadt_6; Break ; // Duplicate burst Block Transmission staggered } * Dmaxctl | = (srcmode & 0x04) <2; // Source word or byte * Dmaxctl | = (srcmode & 0x03) <8; // Source Address Change Mode * Dmaxctl | = (dstmode & 0x04) <3; // The target word or byte * Dmaxctl | = (dstmode & 0x03) <10; // Destination Address Change Mode * Dmaxsa = SRC; * dmaxda = DST; * dmaxsz = size; * dmaxctl | = dmaen; // DMA enabling }

Functions are troublesome. Each register is set based on parameters. Dmactl0 = trigger <(Channel <2); this is the reference source for setting the corresponding channel. If you are not clear about it, you can check the register content of dmactl0;Switch (The channel) Statement sets the registers pointed to by the corresponding pointer according to the channel, and then corresponding to the set parameters.

When set to non-repetitive mode, you need to reset the dmaen. This program implements the function dmareenable:

VoidDmareenable (CharChannel ){Switch(Channel)// Enable the corresponding channel{Case0: dma0ctl | = dmaen;Break;// 0-ChannelCase1: dma1ctl | = dmaen;Break;// Channel 1Case2: dma2ctl | = dmaen;Break;// 2 channels}}
 

This function is relatively simple. It only sets the dmaen bit of the corresponding channel based on the input parameters.

When it is set to software-triggered, the software must start the DMA program as follows:

VoidDmastart (CharChannel ){Switch(Channel)// Enable the corresponding channel{Case0: dma0ctl | = dmareq;Break;// 0-ChannelCase1: dma1ctl | = dmareq;Break;// Channel 1Case2: dma2ctl | = dmareq;Break;// 2 channels}}
 

This is similar to the previous function: just set a control bit. The function is very simple and will not be explained.

There are so many program implementations. For details, you can download the library in the attachment. The program annotations are very detailed.

6. Example:

When using this program, the steps are the same as the original one: add the DMA. c file to the project, and then the source file contains the DMA. h header file.

The example program is as follows:

# Include<Rjx16x. h># Include"DMA. H"Unsigned intA [5] = {8693,5689, 2356,23565, 5656 };Unsigned intB [5];VoidMain (Void){// Stop watchdog timer to prevent time out ResetWdtctl = wdtpw + wdthold; clkinit ();// Block transfer, 5 characters (16 bits) A-> BDmainit (0, 0x00,'B', 3, 3 ,(Unsigned int) ,(Unsigned int) B, 5); dmastart (0 );// If you need to transfer the data again without changing the settings, you only need to call dmareenable to start the transmission again. // if it is a duplicate block transfer, you do not need to re-enable dmareenable to start directly. // here only shows how to use it. In actual application, select an appropriate trigger source as needed. //Lpm0 ;}
 

The example program completes the function very easily, just assigning the value of an array to another array. The array address is the required type (unsigned 16-bit) for forced conversion of the array name, and the input function initialization settings. For ease of use, set it to software startup.

The running effect is as follows:

After one step is complete and the DMA transmission is started, the result is displayed, indicating that the speed of the DMA data transmission is very fast.

DMA can be used in programs with high speed requirements. For example, DMA, coupled with the hardware multiplier and adc12 module, can easily implement a high-frequency digital filtering solution.

Attachment: Library

Author:Give me a drink

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