MTK serial drive part-1

/*************************************** **************************************
* Copyright statement:
*--------------------
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**************************************** *************************************/

/*************************************** **************************************
*
* Filename:
*---------
* Bl_uart.c
*
* Project:
*--------
* NFB-bootloader
*
* Description:
*------------
* UART driver.
*
* Author:
*-------
*-------
*
* ===================================================== ============================================
* History
* Below this line, this part is controlled by PVCs VM. Do not modify !!
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* Upper this line, this part is controlled by PVCs VM. Do not modify !!
* ===================================================== ============================================
**************************************** ************************************/
 
# Include <kal_release.h>
# Include <bl_uart_h1_h>
# Include <bl_uart_sw.h>

// 52 MHz based!
// 9: 115200 BPS
// 8: 57600 BPS
# Define uart_baud_rate 9

Kal_uint16 uart_baud_table [10] = {
# If defined (mt6268a) | defined (mt6268)

# If (defined (mcu_245_76m) | defined (mcu_122_88m) | defined (mcu_61_44m ))
34909,128 00, 3200,160 0, 800,400,200,100, 67, 33 };
# Elif defined (mcu_30_72m)
17455,640 0, 1600,800,400,200,100, 50, 33, 17 };
# Else
8727,320 0, 800,400,200,100, 50, 25, 17, 8 };
# Endif

# Else
// # If (defined (mpll_52mhz) | defined (mpll_0000mhz ))
# If (defined (mcu_52m) | defined (mcu_1_m) | defined (mcu_208m ))
29544,108 34, 2708,135 2, 676,340,168, 84, 56, 28 };
# Else
14773,541 7, 1354,677,339,169, 85, 42, 28, 14 };
# Endif

# Endif/* defined (mt6268a) | defined (mt6268 )*/

/*************************************** *******************
Description: UART register read write module
Input: Address to access, data to be written for write operation.
Output: return data for read operation.
**************************************** *******************/

Void uart_writereg (kal_uint32 ADDR, kal_uint16 data)
{
* (Volatile kal_uint8 *) ADDR = (kal_uint8) data;
}

Kal_uint16 uart_readreg (kal_uint32 ADDR)
{
Volatile kal_uint8 TMP;
TMP = * (volatile kal_uint8 *) ADDR;
Return (kal_uint16) TMP;
}

/*************************************** *******************
Description: UART put single/multiple bytes
Input: 8-bits data to be sent
Output: non
**************************************** *******************/

Void putuartbyte (kal_uint8 data)
{
Volatile kal_uint16 LSR;

While (1)
{
LSR = uart_readreg (uart1_lsr );
If (LSR & uart_lsr_thre)
{
Uart_writereg (uart+thr, (kal_uint16) data );
Break;
}
}
}

/*************************************** *******************
Description: Checking end of transferring
Input: non
Output: non
**************************************** *******************/

Void checkuartsendend (void)
{
Kal_uint16 LSR;
Kal_uint16 timeout = 0 xFFFF;

While (timeout --)
{
LSR = uart_readreg (uart1_lsr );
If (LSR & uart_lsr_temt)
Break;
}
}

/*************************************** *******************
Description: UART Initialization
Input: non
Output: non
**************************************** *******************/

Void uart_init (void)
{
Volatile kal_uint16 TMP;

// Setup 8-n-1, (uart_wls_8 | uart_none_parity | uart_0000stop) = 0x03
Uart_writereg (uart+lcr, 0x0003 );

// Set baudrate
TMP = uart_readreg (uart+lcr );
TMP | = uart_lcr_dlab;
Uart_writereg (uart+lcr, TMP );
// Config by uart_baud_rate (9: 115200)
Uart_writereg (uart1_dll, uart_baud_table [uart_baud_rate] & 0xff );
Uart_writereg (uart1_dlh, uart_baud_table [uart_baud_rate]> 8 );
Uart_writereg (uart+lcr, 0x0003 );
// Enable FIFO, and Rx trigger level = 16 bytes, flush Tx, RX FIFO
// (Uart_fcr_fifoen | uart_fcr_4byte_level | uart_fcr_rfr | uart_fcr_tfr) = 0x47
Uart_writereg (uart+fcr, 0x0047 );

// DTR, RTS is on, data will be coming, output2 is high
Uart_writereg (uartw.mcr, (kal_uint16) 0x0003 );

// Uart1_ier, enable RDA, RLS, MS, disable thr interrupt
// Uart_writereg (uart1_ier, uart_ier_rda );
Uart_writereg (uart1_ier, ier_hw_normalints );
// Irqsensititive (irq_uart+code, level_sensitive );
// Irqunmask (irq_uart#code );

For (TMP = 0; TMP <0xff; TMP ++ );
}