MTK serial drive part-2

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/*************************************** ****************************************
* Filename:
*---------
* Bl_uart_h1_h
*
* Project:
*--------
* NFB-bootloader
*
* Description:
*------------
* This file is intends for UART driver.
*
* Author:
*-------
*-------
*
* ===================================================== ============================================
* History
* Below this line, this part is controlled by PVCs VM. Do not modify !!
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*------------------------------------------------------------------------------
* Upper this line, this part is controlled by PVCs VM. Do not modify !!
* ===================================================== ============================================
**************************************** ************************************/
 
# Ifndef _ bootloader_uart_hw_h
# DEFINE _ bootloader_uart_hw_h

# If defined (_ application_processor __)

# If defined (mt6516)
# Define uart+base 0x80023000
# Define uart2_base 0x80024000
# Endif/* mt6516 */

# Else/* _ application_processor __*/

# If defined (mt6238) | defined (mt6235) | defined (mt6239) | defined (mt6235b) | defined (mt6516) | defined (mt6253)
# Define uart+base 0x81030000
# Define uart2_base 0x81040000
# Elif defined (mt6268a) | defined (mt6268)
# Define uart+base 0x85030000
# Define uart2_base 0x85040000
# Else/* mt6228 | mt6229 | mt6230 | mt6225 */
# Define uart+base 0x80130000
# Define uart2_base 0x80180000
# Endif

# Endif/* _ application_processor __*/

// Uart1 MMP address
# Define uart+rbr (uart+base + 0x0)/* read only */
# Define uart+thr (uart+base + 0x0)/* write only */
# Define uart1_ier (uart+base + 0x4)
# Define uart+iir (uart+base + 0x8)/* read only */
# Define uart+fcr (uart+base + 0x8)/* write only */
# Define uart+lcr (uart+base + 0xc)
# Define uart+mcr (uart+base + 0x10)
# Define uart+lsr (uart+base + 0x14)
# Define uart+msr (uart+base + 0x18)
# Define uart+scr (uart+base + 0x1c)
# Define uart+dll (uart+base + 0x0)
# Define uart+dlh (uart+base + 0x4)
# Define uart+efr (uart+base + 0x8)/* only when LCR = 0xbf */
# Define uart+xon1 (uart+base + 0x10)/* only when LCR = 0xbf */
# Define uart+xon2 (uart+base + 0x14)/* only when LCR = 0xbf */
# Define uart+xoff1 (uart+base + 0x18)/* only when LCR = 0xbf */
# Define uart+xoff2 (uart+base + 0x1c)/* only when LCR = 0xbf */
# Define uart+speed (uart+base + 0x24)

// Uart2 MMP address
# Define uart2_rbr (uart2_base + 0x0)/* read only */
# Define uart2_thr (uart2_base + 0x0)/* write only */
# Define uart2_ier (uart2_base + 0x4)
# Define uart2_iir (uart2_base + 0x8)/* read only */
# Define uart2_fcr (uart2_base + 0x8)/* write only */
# Define uart2_lcr (uart2_base + 0xc)
# Define uart2_mcr (uart2_base + 0x10)
# Define uart2_lsr (uart2_base + 0x14)
# Define uart2_msr (uart2_base + 0x18)
# Define uart2_scr (uart2_base + 0x1c)
# Define uart2_dll (uart2_base + 0x0)
# Define uart2_dlh (uart2_base + 0x4)
# Define uart2_efr (uart2_base + 0x8)/* only when LCR = 0xbf */
# Define uart2_xon1 (uart2_base + 0x10)/* only when LCR = 0xbf */
# Define uart2_xon2 (uart2_base + 0x14)/* only when LCR = 0xbf */
# Define uart2_xoff1 (uart2_base + 0x18)/* only when LCR = 0xbf */
# Define uart2_xoff2 (uart2_base + 0x1c)/* only when LCR = 0xbf */
# Define uart2_speed (uart2_base + 0x24)

// Uart3 MMP address
# Define uart3_rbr (uart3_base + 0x0)/* read only */
# Define uart3_thr (uart3_base + 0x0)/* write only */
# Define uart3_ier (uart3_base + 0x4)
# Define uart3_iir (uart3_base + 0x8)/* read only */
# Define uart3_fcr (uart3_base + 0x8)/* write only */
# Define uart3_lcr (uart3_base + 0xc)
# Define uart3_mcr (uart3_base + 0x10)
# Define uart3_lsr (uart3_base + 0x14)
# Define uart3_msr (uart3_base + 0x18)
# Define uart3_scr (uart3_base + 0x1c)
# Define uart3_dll (uart3_base + 0x0)
# Define uart3_dlh (uart3_base + 0x4)
# Define uart3_efr (uart3_base + 0x8)/* only when LCR = 0xbf */
# Define uart3_xon1 (uart3_base + 0x10)/* only when LCR = 0xbf */
# Define uart3_xon2 (uart3_base + 0x14)/* only when LCR = 0xbf */
# Define uart3_xoff1 (uart3_base + 0x18)/* only when LCR = 0xbf */
# Define uart3_xoff2 (uart3_base + 0x1c)/* only when LCR = 0xbf */

// Ier
# Define uart_ier_erbfi 0x0001
# Define uart_ier_etbei 0x0002
# Define uart_ier_elsi 0x0004
# Define uart_ier_edssi 0x0008
# Define uart_ier_x offi 0x0020
# Define uart_ier_rtsi 0x0040
# Define uart_ier_ctsi 0x0080
# Define ier_hw_normalints 0x000d
# Define ier_hw_allints 0x000f
# Define ier_sw_normalints 0x002d
# Define ier_sw_allints 0x002f
# Define uart_ier_alloff 0x0000

// FCR
# Define uart_fcr_1_oen 0x0001
# Define uart_fcr_clrr 0x0002
# Define uart_fcr_clrt 0x0004
# Define uart_fcr_1_oini 0x0007
# Define uart_fcr_rx1byte_level 0x0000
# Define uart_fcr_rx16byte_level 0x0040
# Define uart_fcr_rx32byte_level 0x0080
# Define uart_fcr_rx62byte_level 0x00c0

# Define uart_fcr_tx1byte_level 0x0000
# Define uart_fcr_tx16byte_level 0x0010
# Define uart_fcr_tx32byte_level 0x0020
# Define uart_fcr_tx62byte_level 0x0030

# Define uart_fcr_normal (uart_fcr_tx16byte_level | uart_fcr_rx32byte_level | uart_fcr_1_oini)

// IIR, Ro
# Define uart_iir_invalid 0x0001
# Define uart_iir_rls 0x0006 // reset ER line status
# Define uart_iir_rda 0x0004 // receive data available
# Define uart_iir_cti 0x000c // character timeout indicator
# Define uart_iir_thre 0x0002 // transmit holding register empty
# Define uart_iir_ms 0x0000 // check modem Status Register
# Define uart_iir_swflowctrl 0x0010 // receive xoff characters
# Define uart_iir_hwflowctrl 0x0020 // cts or RTS rising edge
# Define uart_iir_kerberos_enabled 0x00c0
# Define uart_iir_no_interrupt_pending 0x0001
# Define uart_iir_int_mask 0x001f

/// ============================================ ======================================
// WLS
# Define uart_wls_8 0x0003
# Define uart_wls_7 0x0002
# Define uart_wls_6 0x0001
# Define uart_wls_5 0x0000
# Define uart_data_mask 0x0003

// Parity
# Define uart_none_parity 0x0000
# Define uart_odd_partity 0x0008
# Define uart_even_parity 0x0018
# Define uart_mark_parity 0x0028
# Define uart_space_parity 0x0038
# Define uart_parity_mask 0x0038

// Stop bits
# Define uart_1_stop 0x0000
# Define uart_rj5_stop 0x0004 // only valid for 5 data bits
# Define uart_2_stop 0x0004
# Define uart_stop_mask 0x0004

# Define uart_lcr_dlab 0x0080

/// ============================================ ======================================

// MCR
# Define uart_mcr_dtr 0x0001
# Define uart_mcr_arg 0x0002
# Define uart_mcr_loopb 0x0010
# Define uart_mcr_ire 0x0040 // enable IrDA modulation/Demodulation
# Define uart_mcr_x off 0x0080
# Define uart_mcr_normal (uart_mcr_dtr | uart_mcr_rts)

// LSR
# Define uart_lsr_dr 0x0001
# Define uart_lsr_oe 0x0002
# Define uart_lsr_pe 0x0004
# Define uart_lsr_fe 0x0008
# Define uart_lsr_bi 0x0010
# Define uart_lsr_thre 0x0020
# Define uart_lsr_temt 0x0040
# Define uart_lsr_1_oerr 0x0080

// MSR
# Define uart_msr_dcts 0x0001
# Define uart_msr_ddsr 0x0002
# Define uart_msr_teri 0x0004
# Define uart_msr_ddcd 0x0008
# Define uart_msr_cts 0x0010
# Define uart_msr_dsr 0x0020
# Define uart_msr_ri 0x0040
# Define uart_msr_dcd 0x0080

// DLL
// DLM
// EFR
# Define uart_efr_autocts 0x0080
# Define uart_efr_autorts 0x0040
# Define uart_efr_enchance 0x0010
# Define uart_efr_swctrlmask 0x000f
# Define uart_efr_noswflowctrl 0x0000
# Define uart_efr_alloff 0x0000
# Define uart_efr_autortscts 0x00c0

// Tx/RX xon1/xoff1 as flow control word
# Define uart_efr_swflowctrlx1 0x000a

// Tx/RX xon2/xoff2 as flow control word
# Define uart_efr_swflowctrlx2 0x0005

// Tx/RX xon1 & xon2/xoff1 & xoff2 as flow control word
# Define uart_efr_swflowctrlxall 0x000f

# Define uart_tx1_o_depth 48
# Define uart_rx1_o_depth 62

# Endif