NAND Flash Bare Board programming

NAND Flash According to my understanding, on the Development Board is similar to our use of the computer's hard disk, used to save the system running operating system, applications, data, etc., after power down can also be permanently saved data (excluding temporary data). By controlling or configuring the controller registers of NAND Flash, you can perform the operation on NAND: including reading, writing, erasing, etc.

The control and configuration of these registers is based on the board schematic, user manual and NAND flash chip manual instructions to configure.

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Through the schematic diagram, it can be seen that the data transmission between NAND flash and CPU is mainly through the Lddata0~7 8 pin line, wherein the transmission of "data" may be the address, data, or command, which depends on the CLE, Ale pin State selection.

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For the transmission of the command, the main is to write the Nfcmd register above the corresponding command value, but this command is carried out in two cycles.

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And for data transmission, in the transmission mode, the transmission of data is to be based on the above format to carry out transmission, divided into 5 cycles, each cycle of data transmission is very fastidious, which requires a smart algorithm in line with this format (in the following code).

After understanding these commands and the data transfer format, the specific registers are configured accordingly. The first thing to do is to describe the functions of these registers (each register is described in the data sheet):

(1) nfconf: Used to set timing parameters, set the bit width.

(2) Nfcmd: command register.

(3) NFADDR: Address register.

(4) Nfdata: Data register for reading and writing data.

(5) Nfstat: status register, only use the lowest 1 bits, indicate whether busy.

Programming Examples :

The implementation runs from the NAND flash to the SDRAM, which involves programming the startup code, initializing the memory controller, and reading and copying the data on the NAND flash. (only part of the core code is shown)

Head. S

.text.global    _start_start:    ldr sp,=4096             @ Setting the Stack     bl disable_watch_dog     @ off watchdog     bl set_mem                 @ setting up the memory controller     bl nand_init              @nand Initialization     ldr  r0,=0x30000000    ldr r1,=4096    ldr r2,=4096              @ Transfer Parameters     bl  nand_read            @ copying from NAND      ldr sp,=0x38000000    ldr lr, =halt           @ SetReset return address     ldr pc, =main  halt:    b halt 

NAND.C

typedef struct s3c2440_nand  {    unsigned int nfconf;     unsigned int NFCONT;    unsigned int NFCMMD;     unsigned int NFADDR;    unsigned int NFDATA;     unsigned int NFMECCD0;    unsigned int NFMECCD1;     unsigned int NFSECCD;    unsigned int NFSTAT;     unsigned int NFESTAT0;    unsigned int  Nfestat1;    unsigned int nfmecc0;    unsigned int  nfmecc1;    unsigned int nfsecc;    unsigned int &NBSP;NFSBLK;&NBSP;&NBSP;&NBSP;&NBSP;UNSIGNED&NBSP;INT&NBSP;NFEBLK;} s3c2440_nand;//defines the starting address of the Nandflash controller static s3c2440_nand* nand_base =  (s3c2440_nand*) 0x4e000000;//void select_chip_or_not (Int flag)//0 no chip selection, 1-piece selection {     if (flag == 1)     {         nand_base->nfcont |=  (0x1<<1); &NBSP;&NBSP;&NBSP;&NBSP;}&NBSP;&NBSP;&NBSP;&NBSP;IF (flag  == 0)     {        nand_base->nfcont  &= ~ (0x1<<1);     }}void write_command (unsigned char  CMD) {     volatile unsigned char *p =  (volatile  unsigned char *) &nand_base->nfcmmd;    *p = cmd;} VOID&NBSP;WRITE_ADDR (UNSIGNED&NBSP;INT&NBSP;ADDR) {    int i;     volatile unsigned char* p =  (volatile unsigned char *) nand_base-> nfaddr;    *p =  Addr & 0xff;    for (i=0; i<10; i++);     *p  =  (addr >> 9)  & 0xff;    for (i=0; i<10;  i++);    *p =  (addr >> 17)  & 0xff;     for (i=0; i<10; i++);    *p =  (addr >>  25)  & 0xff;    for (i=0; i<10; i++);} Wait Nand flash ready void wait_ldle (void) {    volatile unsigned char*  p =  (volatile unsigned char*) Nand_base->nfstat;    int flag  = *p & 1;    while (!flag)     {         int i;        for (i=0;i<20 ; i++);     }}unsigned&nbsP;char read_data (void) {    volatile unsigned char *p=  (volatile  unsigned char*) Nand_base->nfdata;    return *p;} Void nand_read (unsigned char* buf,unsigned char base_addr,unsigned int size ) {    int i,j;    //Tablet select     select_chip_or_not ( 1);     //copy Data     for (i=base_addr;i<base_addr+size;)      {        write_command (0);//Send Read command      &NBSP;&NBSP;&NBSP;&NBSP;WRITE_ADDR (i);    //send address          Write_command (0x30);         wait_ldle ();         for (j=0;j<512;j++,i++)         {          &nbsP;  *buf = read_data ();  //read data, read one page at a time (512 bytes)              buf++;        }     }    select_chip_or_not (0);//Cancel Chip selection}void nand_reset (void) {     select_chip_or_not (1);//Chip Selection     write_command (0xff);     wait_ldle ( );     select_chip_or_not (0);} Void nand_init (void) {        nand_base->nfconf =  (0 &LT;&LT;12) | (3<<8) | (0<<4);    nand_base->nfcont =  (1<<4) | (1<<1) | (1<<0);     nand_reset ();}

and the next makefile.

OBJS: = HEAD.O init.o nand.o main.onand.bin: $ (OBJS) arm-linux-ld-tnand.lds $^-o nand_elf arm-linux-objcopy-o bi Nary-s nand_elf [email protected]%.o:%. S arm-linux-gcc-c $<-o [email protected]%.o:%.c arm-linux-gcc-c $<-o [email protected]clean:rm-f n And.bin *.O nand_elf

Usually write makefile not the same, here used a link script called Nand.lds, this is mainly for the test to make the compiled program in the link when the address and the theoretical operating address are different and not on the same storage device, convenient to see the test results.

Nand.lds

SECTIONS {First 0x00000000: {head.o init.o NAND.O} second 0x30000000:at (4096) {MAIN.O}}

The first paragraph on the link script is put head. S init.c NAND.C compiled content, starting from 0 address storage and execution, while MAIN.O is required from the NAND flash manually copied to the SDRAM to execute.

The effect of the implementation

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This article is from the "June Feng Eureka" blog, please be sure to keep this source http://10274409.blog.51cto.com/10264409/1771635

NAND Flash Bare Board programming