Nand Flash Fundamentals

Before understanding the basic principle of random access memory, which is mainly through the charge and discharge of the capacitor to ensure the data read and write, when the power loss, the data is lost, this section we mainly learn the basic composition and principle of Flash. Now flash in the embedded system and the status of the hard disk on the PC similar to the system used to save the system, data and application sequence, and memory loss after the power, it can be permanently saved after the drop point.

　　1. Flash Memory storage Unit

　For flash memory, we commonly have SLC and MLC two kinds, subdivision also ESLC and EMLC, etc., because flash type a voltage element, so it is different voltage range to represent different data, now look at the difference between the two.
1) SLC (single-level cell): Unfiltered storage unit, which is the flash memory of each storage unit to store 1bit of data, stored data on behalf of 0 or 1 is based on the Vth voltage threshold to determine, for Flash write, is to charge it, So that its voltage value exceeds the voltage point A, the storage unit is represented as 0 (programmed), if there is no charge or voltage threshold is less than a point, 1 (has been erased). Mainly for military, enterprise-class applications, with high-speed write, low error rate and durability.

　2) MLC (multi-level cell) multi-stage storage unit, which is to store 2bit of data per storage unit, the data stored is "00", "01", "10", "11" is also based on the threshold of voltage determination, which is divided into 4 parts. Relative to the SLC,MLC of each unit is 2bit, then its capacity will be larger, while its storage unit to hold more data, then its structure is relatively complex, the opportunity for error is also relatively large. Mainly for consumer-grade applications, with high capacity, low cost, for USB flash memory, mobile phones, digital cameras and other memory cards.

　　2. Flash internal principle

By its stored particle structure, know the flash-type voltage element, which depends on the voltage to store the data, then look at its structure and working principle. The internal storage structure of the flash memory is a metal-oxide layer-semiconductor-FET (MOSFET): The source, drain and gate, which works similar to the FET, is the voltage using the control source and the drain between the fault, the difference is that the FET is a single gate structure, and flash-type dual-gate structure, There is also a floating gate between the gate and the silicon substrate, and the floating gate is composed of a nitride sandwiched between the silica material.

1) for the write of flash memory, that is, to control the gate to charge, the gate pressure, so that the more charge of the floating gate storage, exceeding the threshold value, it means 0

2) for the flash of the erase, that is, the floating gate discharge, below the threshold value, it means 1

After understanding the fundamentals of flash storage data, let's look at the hardware composition and how it works for the k9f1g08x0c chip. The pins are distributed as follows

Signal Name	Pin Name	Type	Describe
Data cable	I/o0 ~ I/o7	Inputs/outputs	Used to transfer command/address/data, only used to output data during read operations
Command latch Enable	CLE	Input	When the CLE is high, on the we# rising edge, the command is latched to the command register via i/o[7:0], and when the command is not transmitted, the CLE should be low
Address latch Enable	ALE	Input	When the ale is high, on the we# falling edge, address information via i/o[7:0] latches the address register inside the chip. If the transmission is not address information, the ALE should be low
Chip selection	ce#	Input	ce# can become invalid once the device enters program or erase operation
Read Enable	re#	Input
Write enable	we#	Input	On we# Rising edge Command/address/data latch
Write protection	wp#	Input	When it's low, all program and erase are banned
Ready/Busy status	R/b		Open-collector output. The external requires a pull-up resistor, which indicates that the chip is in program or erase operation. During a read operation, the data is transferred from the array to the serial data register, and once these operations are complete, r/b# returns to the High-z state.
Power	Vcc
To	Vss

from the above, Nandflash's peripheral pin is very small, no address line, only the data line, relative to the data line and address line Norflash, greatly reducing the number of pins, making the chip smaller, hardware design is simpler. Now the data line is multiplexed, that is, you can pass data, you can also pass the address, you can also preach commands, then how to do it? What does the hardware need to pass in order to differentiate the current? Design the Cle/ale command, so you must first send a Cle/ale command, tell the controller, I am now the command or address, so that can identify and do the corresponding processing. We understand the connection of hardware, then how to store flash? Here's a look at the storage layout of this chip

It can be seen from the figure that a NAND flash is a device, and its data storage hierarchy is:

1. One device = 1024 blocks (Blocks), and the block is also the smallest unit of the NAND Flash erase operation.

2.1 blocks (block) = 64 pages (pages), the smallest unit of NAND flash write, for each page, by block area and idle area. Data area, also easy to understand, is to store some data, and for the idle area, is generally called OOB (out of Band), this region is based on the hardware characteristics of NAND flash design, NAND flash in the data read and write is easy to error, so in order to ensure the correctness of the data, There must be a corresponding mechanism for detection and correction, this mechanism is called ECC, so the redundant area is designed to place the checksum value of the data.

3.1 pages (page) = data block Size (2K) +oob block Size (64Bytes)

So by the above we can calculate how to access a physical address: block Size * Block number + Page Size * page number + in-page address.

From the hardware diagram, for k9f1g08x0c this chip, its capacity is 132MB, then should need 28 address first, and now only 8 address line, for NAND flash imported the concept of address cycle, for the Flash, So it takes 4 cycles: 2 column address (columns) period and 2 line address (row) period. From the following functional block diagram, for the column address A0--a11, is the page address, the address range is 0--4094, and the page address (2k+64), in fact, for the page address, in fact, only need to a0-a10, and for the more A11, is used to represent the OOB area of the page. So for a12-a27, it is used to indicate which page number belongs to which block and block.

Through the previous explanation of the basic principles of NAND flash, let's look at how to operate NAND flash, below is the command format supported by K9F1G08X0C.

Is the complete process of sending a command/address/data

The timing diagram shows that there are a lot of time parameters, when setting up the NAND flash controller, you need to confirm whether these time parameters are in the appropriate range, for the control command is through the above several basic command combination, at this time for NAND flash basic control methods and principles have been introduced.

Nand Flash Fundamentals