Paging memory management for the operating system 1

1. The core of paging memory management is: translation of pages.

For any virtual page, will the system know if the page is in physical memory? If so, which is the corresponding physical page? If not, a page fault is generated and the virtual pages are transferred from disk to memory and the physical page number assigned to it is returned. The mapping of virtual pages to physical pages, this translation process is done by the Memory management Unit MMU. The MMU receives the virtual address sent by the CPU, translates it to a physical address and sends it to memory. The MMU's translation of the virtual address is just the translation of the page number, and for the offset value it does nothing, because the virtual page table is exactly the same size as the physical page table, and the offset value in the virtual page is exactly the same as the offset value in the physical page, so no translation is required.

2. What is the position of the page table in the paging management system?

The page table records the same number of bars as the number of virtual pages. For a virtual address of 32-bit addressing, if the page size is 4KB, the page table can have up to 1,048,576 record bars. The memory management unit relies on the page table to perform all the administrative activities related to the page, such as determining whether a page number is in memory, whether the page is protected, and whether the page is illegal.

3. What does the page table record?

4. Page translation process?

5. What are the drawbacks and workarounds for paging memory management?

A page table can be large and take up a lot of memory space, such as 1,048,576 pages of records, each of which takes up more than one byte, so that a page table occupies a large memory space.

1) Multi-level page table

2) reverse Page Table

6. How to improve translation efficiency?

If you use a single-level page table, each memory access becomes two memory accesses, the page table is accessed, the actual physical memory is accessed, and if you use a multilevel page table or a Reverse page table, each memory access becomes more memory-accessible and less efficient. To improve the efficiency of this memory translation, we have come up with some methods.

In a period of time, the address space to be accessed by the program has a little space limitations, if a page is accessed, some pages are very likely to be accessed, so that we can have the translation of these pages in the cache, so that can greatly improve system efficiency.

tlb is typically provided by the CPU manufacturer, but the tlb replacement algorithm may be improved by the operating system.

7. Missing pages interrupt processing?

8. Lock the page: If a page is important, you can lock it to prevent unnecessary page substitutions.

9. A fragmented space within a process is called an internal space, and the larger the page, the greater the internal fragmentation is likely to be. The smaller the page, the larger the size of the page table, so the size of the page is balanced between the internal fragmentation and the page table size.

10. What is the concept of memory jitter?

When the page is changed, if the replacement page is a page that will be accessed very quickly, then a new fault will occur soon after the break is interrupted, and the worst case is that each new access is to a page that is not in memory, that is, each memory access will cause a fault So every memory access actually becomes disk access, the disk access speed may be millions of times times slower than memory, so the efficiency of the whole system drops sharply, this phenomenon is called memory jitter. The memory jitter is that the system can hardly see any progress, and most of the CPU resources will be consumed on the page fault.

Paging memory management for the operating system 1