PCB wiring specifications (Huawei)

 

PCB wiring specifications (Huawei) () Design Process

A. Create a network table

1. the network table is the schematic diagram and PCB interface file. The PCB designer should select the correct network table based on the principle diagram and the features of the PCB design tool to create a network Table meeting the requirements.

2. During the process of creating a network table, the schematic design tool should actively assist the schematic designer in troubleshooting errors according to the features of the schematic design tool. Ensure the correctness and integrity of the network table.

3. Determine the encapsulation of the device (PCB footprint ).

4. Create a PCB design File Based on the board structure diagram or the corresponding standard board frame;

Note that the position of the coordinate origin of the board is correctly selected. The origin setting principle is as follows:

A. the intersection of the extended cable on the left and bottom of the Board.

B. The first pad in the lower left corner of the Board.

Round Corner around the board frame, with a radius of 5mm. For special situations, see structure design requirements.

B. Layout

1. Set the size of the panel and frame according to the structure diagram, arrange the installation holes, connectors, and other devices to be located according to the structural elements, and assign the devices unmovable attributes. Dimensional labeling is performed according to the process design specifications.

2. According to the structure chart and the clamping side required during production and processing, set the prohibited wiring area and the prohibited layout area of the printed board. Set a prohibited wiring area according to the special requirements of some components.

3. Select a processing process based on PCB performance and processing efficiency.

The optimal sequence of processing technology is: single-side mounting of component surface-component surface stickers, plug-in mixing (component surface plug-in welding surface mounting a wave top forming)-Dual-side mounting-component surface paste plug-in mixing, welding surface mounting.

4. basic layout principles

A. Follow the arrangement principle of "first big, then small, first difficult and then easy", that is, the layout of important unit circuits and core components should be prioritized.

B. The layout should refer to the schematic diagram and arrange the main components according to the main signal flow pattern of the Board.

C. the layout should meet the following requirements as much as possible: the total connection line should be as short as possible, and the key signal line should be the shortest; the high voltage, high current signal should be completely separated from the small current, low voltage weak signal; the analog signal should be separated from the digital signal; high-frequency signals are separated from low-frequency signals, and the interval between high-frequency components must be sufficient.

D. Use symmetric Standard Layout as much as possible for circuit parts of the same structure;

E. Optimize the layout according to the standard of uniform distribution, balanced center of gravity, and beautiful layout;

F. Set the device layout grid. Generally, the grid should be 50--100 mil for IC device layout, and the grid should be no less than 25mil for small-sized surface-mounted devices.

G. If there are special layout requirements, they should be determined after communication between the two parties.

5. the same type of plug-in components should be placed in the direction of X or Y. For the same type of polar discrete elements, efforts should also be made to maintain consistency in the X or Y direction for easy production and testing.

6. heating components should generally be evenly distributed to facilitate the cooling of the board and the whole machine. temperature-sensitive components other than temperature detection components should be kept away from the components with high heat.

7. The arrangement of components should be convenient for debugging and maintenance. That is to say, large components cannot be placed around small components, the elements to be debugged, and sufficient space should be available around the components.

8. For boards produced by wave soldering, both the fastener installation holes and the positioning holes should be non-metallic holes. When the installation hole needs to be grounded, the distribution of ground holes should be used to connect to the ground plane.

9. when the welding surface mounting element adopts the wave soldering production process, the axial direction of the resistance and content should be perpendicular to the transmission direction of the wave soldering, and the resistance arrangement and Sop (PIN distance is greater than or equal to 1.27) the components are parallel to the transmission direction in the axial direction. Active components such as IC, soj, PLCC, and QFP with a pin distance less than 1.27mm (50mil) should not be welded by wave soldering.

10. The distance between BGA and adjacent components is greater than 5mm. The distance between other SMD components is greater than 0.7; the distance between the outer side of the mounted component pad and the outer side of the adjacent plug-in components is greater than 2mm; the PCB with connectors, no plug-in or device is available within 5mm of the crimping connector, and no Mount element or device is available within 5mm of the weld surface.

11. The layout of the IC de-couple capacitor should be as close as possible to the power supply pin of the IC, and the circuit formed between the power supply and the ground should be the shortest.

12. When deploying components, appropriate consideration should be given to the use of the same power supply device should be put together to facilitate future power supply separation.

13. The layout of resistance devices used for impedance matching purposes should be reasonably arranged according to their properties.

The layout of the series matching resistance is close to the drive end of the signal, and the distance is generally no more than mil.

The distribution of matching resistors and capacitors must distinguish the source and terminal of the signal, and the matching of terminals with multiple loads must be at the far end of the signal.

14. After the layout is complete, the assembly drawing is printed for the schematic diagram designer to check the correctness of the device encapsulation, and confirm the signal correspondence between the Board, backboard, and connectors. After confirmation, wiring can be started.

C. Set cabling Constraints

1. Report Design Parameters

After the layout is basically determined, The statistical function of the PCB design tool is used to report Basic parameters such as the number of networks, network density, and average pin density to determine the number of signal cabling layers.

For more information about how to determine the signal layers, see the following empirical data.

Pin Density
Signal Layers
Board Layers

More than 1.0
2
2

0.6-1.0
2
4

0.4-0.6
4
6

0.3-0.4
6
8

0.2-0.3
8
12

<0.2
10
> 14

Note: PIN density is defined as: Board area (square inch)/(total number of Board pins/14)

To determine the number of cabling layers, we also need to consider factors such as the board reliability requirements, signal speed, manufacturing costs, and delivery time.

 

1. The wiring layer is set in the high-speed digital circuit design. The power supply and the formation should be put together as much as possible, and no wiring is arranged in the middle. All cabling layers should be as close as possible to a layer, and the ground plane should preferably be the Strip isolation layer.

To reduce the electromagnetic interference between layer signals, the signal line direction of the adjacent wiring layer should be vertical.

You can design 1-2 impedance control layers as needed. If you need more impedance control layers, you need to negotiate with the PCB manufacturer. The impedance control layer should be clearly marked as required. Distribute the network cables with impedance control requirements on the board on the impedance control layer.

2. factors to consider when setting the line width and line spacing

A. Density of the Board. The higher the density of the Board, the finer the linewidth and narrower the gap.

B. Current Strength of the signal. When the average current of the signal is large, the current that can be carried by the wiring width should be considered. The line width can refer to the following data:

Relationship Between Copper Foil Thickness, strip width and current during PCB design

The current load of Copper Foil with different thicknesses and widths is shown in the following table:

Copper thickness 35um copper thickness 50um copper thickness 70um

 

Copper delta T = 10 deg C copper delta T = 10 deg C copper delta T = 10 deg C

Note:

I. When using copper as a wire through a large current, the carrying capacity of the copper foil width should be selected according to the numerical reduction of 50% in the table.

II. in PCB design and processing, Oz (OZ) is often used as the unit of copper thickness, 1 oz copper thickness is defined as 1 square feet of copper foil within an area of one weight, the corresponding physical thickness is 35um, while the 2oz copper thickness is 70um.

C. circuit operating voltage: the dielectric strength should be considered for the wire spacing setting.

D. reliability requirements. When high reliability requirements are required, wider cabling and large spacing are preferred.

E. Technical restrictions on PCB processing

Advanced Chinese and international

We recommend that you use the minimum line width/spacing of 6mil/6mil 4mil/4mil

Maximum Minimum line width/spacing 4mil/6mil 2mil/2mil

1. Set the hole to pass through the wire hole

The minimum aperture of a plate depends on the thickness of the plate. The aperture ratio of the plate thickness should be less than 5-8.

The aperture optimization series are as follows:

Aperture: 24mil 20mil 16mil 12mil 8mil

Pad diameter: 40mil 35mil 28mil 25mil 20mil

Internal hot Pad Size: 50mil 45mil 40mil 35mil 30mil

Relationship between plate thickness and minimum aperture:

Thickness: 3.0 2.5 2.0 1.6 1.0

Minimum aperture: 24mil 20mil 16mil 12mil 8mil

Blind and buried Holes

 

The blind hole is the guide hole connecting the surface and the inner layer without the whole board. The buried hole is connected between the inner layer and

The guide hole is invisible to the surface of the product Board. For the two types of pass hole size settings, refer to the pass hole.

The PCB processing process should be fully recognized when blind and buried holes are used to avoid

If necessary, negotiate with the PCB supplier.

Test Hole

The test hole refers to the passing hole used for the purpose of ICT testing. It can also be used as a guide hole. In principle, the aperture is not limited. The diameter of the pad should be no less than 25mil, and the center distance between the test holes should not be less than 50mil.

Component welding holes are not recommended as test holes.

2. the special wiring range is used for some special areas on the board, for example, some high-density devices require finer line width, smaller spacing, smaller passing holes, or adjustment of wiring parameters of some networks, you need to confirm and set it before wiring.

3. define and split. the plane layer is generally used for power supply and formation (reference layer) of the circuit. Because different power sources and strata may be used in the circuit, the power supply layer and formation must be separated, the potential difference between different power supplies should be considered for the separation width. When the potential difference is greater than 12 V, the separation width is 50mil. Otherwise, 20-25mil is optional.

B. The integrity of the high-speed signal reflux path should be considered for Plane Separation.
C. When the backflow path of the high-speed signal is damaged, it should be supplemented on other wiring layers. For example, copper foil that can be ground can enclose the signal network to provide the ground loop of the signal.
B. Pre-wiring simulation (layout evaluation, to be expanded)
C. Wiring
1. Wiring priority key signal line priority: power supply, touch small signal, high-speed signal, clock signal, synchronization signal and other key signal priority Wiring
Density first principle: Wiring starts from the device with the most complex connection relationships on the board. Wiring starts from the most intensive area on the board.

2. When the wiring quality meets the design requirements, the Automatic wiring device can be used to improve work efficiency. The following preparations should be completed before the Automatic wiring:

 

Do File)
To better control the quality of cabling, you generally need to define cabling rules in detail before running. These rules can be defined in the graphical interface of the software, but the software provides better control methods, that is, write out the Automatic wiring control file (do file) for the design, and the software runs under the control of this file.

3. Try to provide a dedicated cabling layer for key signals such as clock signal, high-frequency signal, and sensitive signal, and ensure its minimum loop area. If necessary, manually prioritize cabling, shielding, and increasing security spacing. Ensure signal quality. 4. the EMC environment between the power supply layer and the formation is poor, and interference-sensitive signals should be avoided. 5. Networks with impedance control requirements should be arranged on the impedance control layer. 6. PCB design should follow the rules 1) ground circuit rules: Minimum loop rules, that is, the signal line and its loop constitute the ring area as small as possible, the smaller the ring area, the less the external radiation, the less interference it receives. For this rule, the distribution of the ground plane and the important signal must be taken into account when the ground plane is split to prevent problems caused by the ground plane slotted. In the design of the Two-layer board, when sufficient space is left for the power supply, fill the remaining parts with reference, and add some necessary holes to effectively connect the dual-sided signals, ground Line isolation is recommended for some key signals. For some high-frequency designs, the problem of signal loop in the ground plane should be taken into special consideration.

2) tamper Control
Crosstalk refers to mutual interference between different networks on the PCB due to long parallel wiring, mainly due to the distribution of capacitance and distribution inductance between parallel lines. The main measures to overcome crosstalk are:

Increase the distance between parallel cabling and follow the rule.

Insert a ground line between parallel lines.

Reduce the distance between the cabling layer and the ground plane.

3) shield protection
Corresponding to the ground circuit rules, in fact, it is also to minimize the circuit area of the signal, more common in some important signals, such as clock signals, synchronous signals; for some particularly important, particularly high frequency signals, we should consider the use of copper axis cable shielding structure design, will be laid on the upper and lower lines with ground isolation, but also consider how to effectively make the effective combination of the shielding ground and the actual ground plane.

4) cabling direction control rules:
That is, the line direction of the adjacent layer is in a forward structure. Avoid entering different signal lines in the same direction in the adjacent layer to reduce unnecessary inter-layer interference. This situation is hard to avoid due to board structure restrictions (such as some backboards, in particular, when the signal rate is high, the land plane should be considered to isolate each wiring layer, and the land signal line should be isolated from each signal line.

5) Open-Loop inspection rules for cabling:
Generally, a dangling line is not allowed ),

The main purpose is to avoid "antenna effect" and reduce unnecessary interference radiation and acceptance. Otherwise, unpredictable results may be produced.

6) impedance matching check rules:
The wiring width of the same network should be consistent, and the variation of the line width will lead to uneven line characteristic impedance. When the transmission speed is high, reflection will occur. This should be avoided in the design. In some conditions, such as plug-in leads and BGA encapsulation leads in a similar structure, the line width may not be changed, and the valid length of the inconsistent middle part should be minimized.

7) cabling termination network rules:
In high-speed digital circuits, when the latency of PCB cabling is greater than 1/4 of the signal rise time (or fall time), the cabling can be considered as a transmission line, to ensure the correct matching between the input and output impedance of the signal and the impedance of the transmission line, multiple matching methods can be used. The selected matching method is related to the network connection mode and the topological structure of the wiring.

A. for point-to-point (one output corresponds to one input) connections, you can select the start-end series matching or terminal parallel matching. The former has a simple structure, low costs, but high latency. The latter matches well, but the structure is complicated and the cost is high.

B. For point-to-point (one output corresponds to multiple outputs) connections, when the topology of the network is a chrysanthemum link, terminal parallel matching should be selected. When the network is a star structure, you can refer to the point-to-point structure.

Star and Chrysanthemum links are two basic topology structures. Other structures can be considered as the deformation of the basic structure, and some flexible measures can be taken for matching. In practice, cost, power consumption, performance, and other factors should be taken into account. In general, full matching is not pursued, as long as the interference caused by misfit reflection is limited to an acceptable range.

8) Closed-Loop inspection rules:
Prevents signal lines from forming self-loops between different layers. Such problems are prone to occur in the Design of Multi-board, and the self-ring will cause radiation interference.

9) rule for controlling the branch length of a wire:
Control the length of the branch whenever possible. The general requirement is tdelay <= trise/20.

10) cabling resonance rules:
For the design of high-frequency signals, the wiring length must not be an integer multiple of its wavelength to avoid resonance.

11) cabling length control rules:
That is, the short-term rule. During the design, try to make the wiring length as short as possible to reduce interference problems caused by long cabling, especially some important signal lines, such as clock lines, always place the oscillator close to the device. When multiple devices are driven, the network topology should be determined based on the actual situation.

12) chamfer rules:
Acute angle and right angle should be avoided in PCB design,

Produce unnecessary radiation and poor process performance.
13) device decoupling rules:
A. add necessary de-coupling capacitors on the printed version to filter out interference signals on the power supply, so that the power supply signal is stable. In the multi-layer board, the location of the de-coupling capacitor is generally not very high requirements, but for the dual-layer board, the layout of the de-coupling capacitor and the wiring mode of the power supply will directly affect the stability of the entire system, sometimes it is even related to the success or failure of design.

B. in the design of the dual-board, the current should be first filtered by the filter capacitor for use by the device, and the impact of the power noise produced by the device on downstream devices should also be fully considered. Generally, the design of the bus structure is better. In the design, it is also necessary to consider the impact of voltage drops caused by long transmission distance on the device. If necessary, add some power filter loops to avoid potential difference.

C. Whether the de-coupling capacitor can be used correctly in high-speed circuit design is related to the stability of the entire board.

14) device Layout Partitioning/layering rules:
A. The main purpose is to prevent mutual interference between modules at Different Operating frequencies and minimize the wiring length of the high-frequency modules. Usually, the high-frequency part is deployed on the Interface part to reduce the wiring length. Of course, this layout still takes into account the possible interference of the low-frequency signal. At the same time, we also need to take into account the division of the high/low frequency part of the ground plane, usually use the ground separation of the two, and then a single point of connection at the interface.

B. For the hybrid circuit, both analog and digital circuits are arranged on the two sides of the printed board respectively. Different layers are used for wiring, and layers are used for isolation in the middle.

15) isolated copper zone control rules:
The emergence of isolated copper areas will bring about some unpredictable problems. Therefore, connecting isolated copper areas with other signals will help improve the signal quality,
Normally, the isolated copper zone is grounded or deleted. In actual production, the PCB manufacturer adds some copper foil to the vacant part of some boards, which is mainly used to facilitate the printing board processing and also has a certain effect on the prevention of print board warping.

16) integrity rules of power supply and ground layer:
For areas with dense guide holes, it is important to avoid the holes connecting to each other in the blank areas of the power supply and formation to form the division of the plane layer, thus damaging the integrity of the plane layer, this increases the loop area of the signal line in the formation.

17) Overlapping power supply and ground layer rules:
Different power supply layers must avoid overlap in space. The main purpose is to reduce the interference between different power supplies, especially between some power supplies with large voltage differences. The overlapping problem of the power supply plane must be avoided. If it is difficult to avoid this problem, you can consider the mid-interval formation.

18) 3w rules:
In order to reduce the crosstalk between lines, ensure that the line spacing is large enough. When the line center spacing is not less than three times the line width, 70% of the electric field can be maintained without mutual interference. If the electric field reaches 98% without mutual interference, a 10 W interval can be used.

19) 20 h rules:
Because the electric field between the power supply layer and the formation changes, electromagnetic interference is emitted at the edge of the plate. Edge Effect.
The solution is to contract the power supply layer so that the electric field is only transmitted within the connected strata. The Unit is H (medium thickness between power supply and ground). If 20 h is used, 70% of the electric field can be restricted to the edge of the connected strata; 98% H can be used to limit the electric field.

20) Five --- five rules:
When selecting the number of layers of the printed board, that is, when the clock frequency reaches 5 MHz or the pulse rise time is less than 5 NS, the PCB must adopt multiple layers. This is a general rule, sometimes due to cost and other factors, when the dual-laminated structure is used, it is best to make one side of the printed board as a complete ground plane layer.

D. Post-Simulation and Design Optimization (to be supplemented)
E. Process Design Requirements
1. General process design requirements refer to printed circuit CAD process design specifications Q/DKBA-Y001-1999 2. ICT functional board testing requirements

A. for boards in mass production, ICT (in circuit test) is generally required in production. In order to meet the requirements of ICT testing equipment, corresponding processing should be done in PCB design, generally, each network must have at least one test point for the test probe to come into contact. It is called an ICT test point.

B. The number of ICT test points on the PCB must comply with the requirements of ICT test specifications. In the PCB welding surface, the test point can be the solder joint of the device or the passing hole.
C. The minimum size of the solder pad at the detection point is 24 mils (0.6mm), and the minimum distance between the two separate test points is 60 mils (1.5mm ).
D. One board for ICT testing. Two 125mils non-metallic holes should be designed on the diagonal corner of the PCB for ICT testing and positioning.
3. PCB labeling specifications. The precise shape size of the printed board should be indicated in the drilling layer, and no closed dimension can be formed; the size and quantity of all holes should be indicated and whether the holes are metallic.

Ii. Design Review
A. After the design of the review process is completed, the PCB designer or product hardware developer can propose a review of the PCB design quality as needed. For the workflow and review methods, see the PCB design review specification.
B. Self-check items
If you do not need to organize a review team for design review, you can check the following items on your own.
1. Check the high-frequency, high-speed, clock and other fragile signal lines, whether the loop area is the smallest, whether it is away from the interference source, whether there are excess passing holes and winding, and whether there is a broken ground partition.
2. check whether there is a signal line passing through the crystal, transformer, optical fiber coupling, and power supply module. Try to avoid Threading under the crystal, especially laying grounding copper skin below the crystal.
3. Check whether the positioning hole and positioning part are consistent with the structure diagram, and whether the ICT positioning hole and SMT positioning cursor are added and comply with the process requirements.
4. Check whether the serial number of the device is properly arranged according to the principle from left to right, and no silk screen overwrites the pad. Check whether the version number of the silk screen conforms to the version upgrade specifications and marks it out.
5. report whether the wiring is finished percent; whether the wiring is wired; whether there is isolated copper skin.
6. Check that the power supply and ground are correctly separated; spof has been processed;
7. Check that the optical painting options of each layer are correct, and that the labels and optical painting names are correct. Only the drawing labels of the drilling layer are required for splicing.
8. output the optical painting file. Use cam350 to check and confirm that the optical painting is generated correctly.

9. Fill in the PCB design (archive) self-check form as required and submit the form together with the design documents to the process designer for Process Review.

10. actively improve problems found during the process review to ensure the manageability, productivity and testability of the Board.

This article is from: I love R & D network (52rd.com)-R & D Base Camp
Http://www.52rd.com/Blog/Detail_RD.Blog_caozhaokun_27769.html: