PCI device configuration space problems

PCI device configuration space problems

Generally speaking, there are two methods to implement the PCI bus interface: one is to use a programmable device CPLD or FPGA, and the other is to use a dedicated interface chip, like the PCI9054 of PLX, ch365. The two have their own advantages and disadvantages. When using programmable devices, you can optimize the interface logic based on specific needs to achieve high performance. Flexibility is its biggest feature. However, due to the complexity of the PCI protocol, it is difficult to implement it, and it is difficult to verify the logical relationship. The latter method solves this design difficulty and saves the development time, so it is quite common.

What I don't know now is that a PCI device can complete the configuration process from power-on to power-on. Take the PCI board developed by the dedicated interface chip as an example. Does the dedicated interface chip provide configuration space? Where is the PCI configuration space (PCI configuration register) and how is it allocated? Generally, the internal register configuration of the dedicated interface chip is to write configuration information (including device identification number, supplierCodeThe local bus space and base address), and then load the E2PROM content to the internal register when power-on. So where are the PCI configuration registers and local configuration registers?

You can solve the problem above. Generally, the registers of the interface chip are divided into PCI configuration registers and local configuration registers. Both can be accessed by the PCI bus and serial EEPROM. The device ID, manufacturer ID, version number, first-zone class code, category code, instruction register, Status Register, and other registers in the PCI configuration register must be implemented on all PCI devices, generally, the operating system can determine the PCI device and load its Driver Based on the contents of these registers.Program. In addition, the PCI configuration register also provides the base address register, which is used together with the local configuration register to relocate the PCI device in the address space. The content of these registers is loaded through the EEPROM.

In the end, the system must allocate a storage space to the PCI Card. When the system accesses this area through the PCI bus, the dedicated interface chip will respond, in addition, the address on the bus is converted to a local address for related operations.

PC has three types of space: memory space, I/O space, and configuration space. The memory space mainly includes memory, memory, extended Rom, and device buffer. It is generally used to store a large amount of data and exchange data blocks. The I/O space mainly includes the control registers and status registers of the device. It is generally used to control and query the working status of the device and exchange a small amount of data. The configuration space is mainly used to provide the system with basic information about the device, and accept the system's control and query of the global status of the device.

To avoid address conflicts, the PCI bus requires that the addresses occupied by each device be relocated. The relocation is implemented by the Base Address Register of the configuration space of the device. Generally, the base address registers of each device are always assigned to different base addresses by the BIOS or operating system to map each device to different address ranges. When necessary, the application can also modify the base address in the base address register to map the device to the specified address range.

Later: according to the specification of PCI Bus 2.1, all PCI devices must implement the PCI configuration space. According to the specification of Version 2.2, each device must configure the address space in addition to the main bus bridge. It can be seen that the configuration space of PCI is implemented on the PCI board. In this case, it refers to the registers on the dedicated interface chip.

Continued: see an article about the dedicated interface chip PCI9054.ArticlePCI9054 provides three physical bus interfaces: PCI bus interface, EEPROM interface, and local bus interface. The PCI bus interface connects the corresponding signals according to the pin distribution conditions defined on the PCI expansion board. The eeprom stores the configuration information of PCI9054, when the system powers up, PCI9054 automatically loads the configuration information, and the BIOS reads and writes the configuration register through the PCI bus to complete various control functions.

Continued: the number of readable and writable bits in the bar determines the size of the bucket. If the size of the read-back space is the same, when the base address is written back, it is only highly writable. For example, if a 10 h write of all F reads back fff00001, it indicates that the memory space is 1 m, and then writing to the inside can only change the three high F, that is, the IO base address of this device must be xxx00001. X is written in.

: The EEPROM is only used to store the register information that needs to be configured. There are two programming methods for the eeprom: first, download the data to the EEPROM and insert it into the card with a dedicated recorder, this method is difficult to modify. Second, it is written online with specialized software, such as plxmon, a special debugging software provided by PLX. Plxmon has the following functions: Detection and selection of PCI bus, check and modification of configuration registers, display, modification and filling of memory space, and read/write of EEPROM content. With this tool, we can modify the content of the eeprom online at any time, greatly improving the efficiency. It is worth noting that the system must be restarted every time the EEPROM is modified, so that the PCI configuration register and the local space configuration register can reload new values.