PLL (Phase Locked Loop)

Basic components of the Phase-Locked Loop
The phase-locked loop (PLL) is a feedback control circuit ). The Phase-Locked Loop uses external input reference signals to control the frequency and phase of internal oscillating signals in the loop. Because the phase-locked loop can automatically track the input signal frequency by the output signal frequency, the phase-locked loop is usually used in the closed loop tracking circuit. When the frequency of the output signal is the same as that of the input signal, the phase difference between the output voltage and the input voltage remains fixed, that is, the phase between the output voltage and the input voltage is locked, which is the origin of the PLL name. The phase-locked loop is usually composed of the Phase Detector (PD, phase
This module consists of three parts: detector, lf, loop filter, and VCO and voltage controlled oscillator.

The phase detector in the Phase-Locked Loop is also called a phase comparator. It detects the phase difference between the input and output signals and converts the detected Phase Difference signal to the UD (t) voltage signal output, after the signal is filtered by a low-pass filter, the control voltage UC (t) of the voltage controlled oscillator is formed to control the frequency of the output signal of the oscillator.

Principle of Phase-Locked Loop
The phase-locked loop is a feedback circuit that synchronizes the clock on the circuit with the phase of an external clock. The PLL synchronizes the phase of the external signal and the phase of the Controlled Crystal Oscillator (vcxo). During the comparison, the Phase-Locked Loop Circuit constantly adjusts the Clock Phase of the local Crystal Oscillator Based on the phase of the external signal until the two signals are synchronized. In the data collection system, the phase-locked loop is a very useful synchronization technology, because through the phase-locked loop, different data collection boards can share the same sampling clock. Therefore, the phases of the local 80 MHz and 20 MHz time bases on all boards are synchronized, so that the sampling clock is also synchronized. Because the sampling clock of each Board is synchronized, data can be collected strictly at the same time.

The programming technology required to synchronize the sampling clock of multiple boards through the phase-locked loop varies depending on the hardware board you are using. For PCI bus-based products (M series data acquisition card, PCI digital devices, etc.), all synchronization is achieved through the clock and trigger line on the rtsi bus; at this time, one Board serves as the main card and outputs its internal clock. Through the rtsi line, other boards can obtain the clock signal for synchronization, the phase-locked loop is synchronized by synchronizing the clock of all boards on the 10 MHz backboard built in PXI.

A simple PLL consists of a frequency reference, a phase detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO. The Frequency Synthesizer Based on the PLL technology will add two divider: one for reducing the baseline frequency, and the other for dividing VCO. It is also easy to combine a phase detector and a charge pump in a function block for analysis (see figure 1 ). The digital frequency divider circuit added on the PLL enables easy adjustment of the operating frequency. The processor simply writes a new divider value to a register located in the PLL, updates the VCO operating frequency, and thus changes the working channel of the wireless device.

Figure 1
PLL is used as a closed-loop control system to compare the phase between the benchmark signal and VCO. The Frequency Synthesizer with the addition of the benchmark and feedback divider is responsible for comparing the two sets of the divider to adjust the phase. This phase is relatively completed in the phase detector. In most systems, this phase detector is a phase and frequency detector. The phase-frequency detector generates an error voltage. The error voltage is approximately linear within the phase error range of ± 2π, and remains constant when the error is greater than ± 2π. The phase-frequency comparator uses this dual-mode operation to generate a faster PLL lock time for high-frequency errors (for example, when the PLL is started during power-on, and avoid locking on the harmonic.

VCO uses the tuning voltage to generate a frequency. VCO can be a module, an IC, or a discrete component. Figure 2 shows a VCO in the max2361 transmitter IC made of an active component. The resonant circuit and variable-capacity diode are external, allowing design engineers to uniquely define if (intermediate frequency) Lo (Local Oscillator) to support specific radio frequency solutions.

Figure 2
--- The loop filter integrates the current pulse generated by the phase-frequency detector's charge pump to generate the tuning voltage applied to VCO. The traditional approach is to increase the tuning voltage from the loop filter (to a greater positive value) so that the VCO phase advances and increases the VCO frequency. Loop filters can be implemented using passive components such as resistors and capacitors, or an operational amplifier. The time constant of the loop filter and the gain of the VCO, phase detector, and divider will set the PLL Bandwidth. The bandwidth of the PLL determines the transient response, baseline parasitic level, and noise filtering. In the bandwidth of the PLL, the phase noise at the output end of the frequency synthesizer is mainly the phase noise of the phase detector. In addition to the bandwidth of the PLL, the output phase noise is mainly derived from the VCO phase noise.

--- The frequency synthesizer PLL reference input is a stable and non-interfering constant frequency signal. Some form of crystal oscillator is used in most radio devices because the phase noise is very low and its frequency is stable and accurate. The PLL will divide the benchmark to provide a lower frequency for the Phase-frequency detector. This low frequency will be used to set the comparison rate of the detector, and a feasible minimum frequency step will be established by increasing the value of the feedback divider with a "1" amplitude. This becomes the frequency resolution of the synthesizer (that is, the frequency step). It should be equal to or less than the channel interval of the radio system being designed. The phase detector and loop filter generate a tuning voltage by using the output of VCO scaled down by the feedback divider.

Input Signal-> phase detector-> low-pass filter-> voltage controlled oscillator-> output signal. The phase detector has two inputs: the input signal and the output signal of the voltage controlled oscillator. When the phase difference and frequency difference between the two are not very large, the output of the phase detector is proportional to the difference between the two input signals, the output of the phase detector is a analog signal. The low-pass filter removes high-frequency clutter and enters the voltage controlled oscillator. The output frequency of the voltage controlled oscillator changes with the change of the input voltage. From the schematic diagram, the PLL is actually a negative feedback system. As long as the input signal is within the normal range, the output signal can be kept up within a certain period of time. When the input signal changes, the process of tracking the input signal is called capture; when the output signal is tracked, it is called locked; when the input signal changes too fast, the output signal cannot be tracked, it is called a lock. The PLL can be used to conveniently achieve N-frequency doubling. The principle is as follows:

Input Signal-> phase detector-> low-pass filter-> voltage controlled oscillator-> output signal
^ | ______ N divider __________ |
In addition, decimal multiplier can be implemented. The principle is as follows:
Input Signal-> phase detector-> low-pass filter-> voltage controlled oscillator-> output signal
^ | ________ N frequency divider/n + 1 frequency divider _________ |
|
| ------ Mode Control----------> |
The mode control module can select whether the divider is at N or N + 1. If it is implemented through the mode control module
9 of the 10 clks are n-division, and 1 CLK is n + 1, the actual output signal frequency is (n + 0.1) ×
Input frequency.
The PLL circuit is essentially a analog circuit, which is completely different from the digital circuit of the ARM kernel, so it is independent of the CPU.
In addition, many CPUs provide separate power supply for the PLL, and require high quality of the PLL power supply.