PLL/DLL concepts

PLL is short for Phase Lock Loop. It is called a "Phase-Locked Loop" in Chinese ". Speaking of the generation of frequency signals, we know that there are many ways to generate a very stable frequency signal by adding voltage to a fixed-shape and large-sized Z crystal, therefore, it is often used as a reference frequency for high-precision instruments. The external frequency on the early computer motherboard is usually directly produced by the Z crystal, the frequency doubling or frequency division circuit is used to obtain signals of different frequencies to coordinate the various circuits of the motherboard. Therefore, the predecessors of the Pentium era often need to replace the crystal when giving the CPU overclocking, it is laborious and troublesome.

In order to generate any high-precision frequency signal in a wide range, the PLL circuit was born. The working principle of the PLL circuit is relatively simple. It consists of a phase detector, a charging pump, a loop filter, and an oscillator (VCO. When the PLL circuit is powered on, the RCL circuit consisting of a variable-capacity diode in VCO starts to oscillate and produces an irregular frequency, the frequency is sent to the phase detector after frequency reduction by the divider circuit and compared with the reference frequency produced by the Z crystal, when the frequency deviation circuit of VCO is set, a correction voltage is generated by the charging pump according to the deviation direction. The voltage is sent to the variable diode in VCO after passing through the loop filter, as the operating voltage of a variable diode changes, the internal capacitance capacity also changes. The VCO oscillation frequency changes and approaches the frequency set by the circuit. Once the two frequency signals are synchronized in phase, the phase error detected by the phase detector is close to 0, and the voltage at both ends of the transformer diode in VCO remains unchanged. The PLL circuit begins to output the set frequency signal and starts to work normally.

Because the frequency of the clock signal output by the PLL circuit can change in a large range, and the adjustment speed is fast, the signal is stable, as long as we change the reference frequency or add different correction voltages, We can freely change the VCO output frequency. This is precisely because of the flexible and convenient features of the PLL circuit, the PLL can be seen in many circuits that require high-quality frequency signals.

The jitter in the datasheet component refers to the internal aperture jitter (Aperture jitter) of the ADC, not the total jitter after the actual sampling system is formed.

 

DLL and PLL are two completely different things used in different places.
DLL-delay locked loop is used in digital circuits to automatically adjust the delay of one channel signal, so that the phase (edge alignment) of the two channels is consistent ), when some digital signals (such as those on the Data Bus) need to be synchronized with the system clock, DLL uses the adjusted clock as the control signal to align the two clock edges (in fact, the adjusted clock lags behind the system clock integer cycle, A signal that is strictly synchronized with the system clock can be generated (for example, the output data is synchronized with the input clock, and the delay of the edge is not affected by the voltage, temperature, and frequency ). PLL -- Phase Locked loop can be used for frequency synthesis (Frequency Synthesizer) in addition to phase tracking (output is the same as input in the same frequency, which is a bit similar to DLL ), the output frequency stability is almost the same as the high-frequency signal of the high-precision low-drift reference signal (such as the temperature fill Crystal Oscillator). At this time, it is a frequency source. The PLL can easily generate high-quality signals of different frequencies. The signal jitter (phase noise in the frequency domain) output by the PLL is related to its loop bandwidth and phase frequency. In general, the lower the bandwidth of the PLL loop, the higher the phase frequency, the smaller the phase noise (the smaller the jitter in the time domain ).
In the actual ADC system, the overall dynamic characteristics of the sampling system mainly depend on the jitter characteristics of the sampling clock. If the frequency requirement is not too high, vcxo is a good choice.
If a variable-frequency and low-jitter clock is required, the PLL-based clock generator is the best choice.