Power Supply Design of Radar Video Signal Simulator Based on TPS54310

Power Supply Design of Radar Video Signal Simulator Based on TPS54310

[Date: 2008-10-13]

Source: foreign electronic components by Liu Donghai, Ren Yongfeng, Li shengkun

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1 Introduction
The radar video signal simulator is an important device for debugging the radar signal processor. It has the analog environment and target video echo signal functions and is used to evaluate the performance of the radar signal processor. Because the analog generation of Radar Video Signals requires a lot of operations, in order to ensure the real-time performance of the system, TI's TMS320C6713B DSP is used as the core component of signal synthesis, the time series logic of the XIUNX Spartan-IIE series FPGA control system is used to increase the flexibility of the system design and simplify the design. Because the MW core voltage of the TMS320C6713B DSP is 1.2 V, the peripheral I/O voltage is 3.3 V, the FPGA kernel voltage is 1.8 V, and the peripheral I/O voltage is 3.3 V, therefore, the power supply system must generate at least three voltages. In addition, the power-on sequence must be considered. If only the DSP or FPGA kernel is used for power supply and the peripheral I/O is not used for power-on, the device will not be damaged, and only the input/output will be unavailable. Otherwise, if the peripheral I/O is powered and the CPU kernel is not powered, the transistor in the buffer/drive part of the device will work in an unknown state, which is very dangerous. Considering that the power consumption of DSP is large, and the system requires that multiple DSPs work simultaneously, linear power supply is used. Therefore, the design of the power supply system is realized by switching power supplies with adjustable output voltage and high conversion rate.

2 Power Supply System Design
The system design uses a low-voltage input, high-current output synchronous PWM Buck Voltage Converter TPS54310 to achieve the power system design, using TPS54310 only a small number of peripheral components, the 60 MΩ MOS switch ensures that the conversion rate is higher than 92% when the output current of 3 A is sustained; the peripheral components are configured to generate a voltage of 0.9 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V. The PWM frequency range is 280 kHz ~ 700 kHz: overload protection using peak current limit and thermal shutdown: strong heat dissipation PWP encapsulation provides better heat dissipation. In addition, TI also provides the SWIFT software design tool for this series of Power Devices to help complete power system design and shorten the R & D cycle.
2.1 kernel voltage and peripheral I/O voltage
The TPS54310 can adjust the resistance of the peripheral resistance to generate 1.2 V, 1.8 V, 3.3 V for the system. The circuit schematic diagram of each voltage is 1 ~ As shown in figure 3, Figure 1 generates a 1.2 V voltage, and figure 2 generates a 1.8 V voltage. Figure 3 generates a 3.3 V voltage because the circuit principles are similar, the following example shows how to adjust the output voltage amplitude to meet the requirements of the power supply system. In Figure 1, you only need to adjust R144 and R150 to meet the following formula:
R144 = (r150 × 0. 890)/(Vo-0.891) (1)
For r150, 10 kΩ is obtained. For example 1, the voltage (VO) of 1.2 V is generated. For example 1, the resistance value of r144 is about 26.1 kΩ.
In this design, the switching frequency of all tps54310 is set to 700 kHz, and the setting of this frequency is calculated using formula 2. Take 1 as an example. The FSW can be set as the switching frequency, and the fan range is 280khz ~ 700 kHz, while requiring sync to remain open.
R136 = (100 KB/FSW) x 500 kHz (2)
Therefore, the resistance of r136 is about 71.5 kb.
The output filter circuit can be calculated using SWIFT software.

2.2 sequential power-on
The system uses TI's TMS320C67-13B DSP and Xilinx's Spartan-IIE series FPGA, both of which require kernel voltage and external same I/O voltage. During power-on, ensure that the kernel is powered on first, and the peripheral I/O is powered on. When power is down, the peripheral I/O power supply should be turned off first, and then the kernel power supply should be turned off.
Realize the sequential power supply between kernel voltage and peripheral I/O voltage. You can adjust the capacitance connected by the tps54310 SS/ena pin and use its pwrgd and SS/ena signals to meet the sequential power supply requirements. The SS/ena pin is grounded with a small capacity capacitor to realize enabling, output delay, and voltage rise delay. The delay time is proportional to the capacity value:

Where: td is the output delay time (s); C (88) is the capacitor (μF) connected to the SS/ENA pin; t (SS) it is the output voltage rise delay time (s ). In the kernel voltage circuit designed by the system, C (SS) = 0.039 μF, 1 and 2 are shown. C (SS) = 0.1 μF, 3 in the peripheral I/O voltage circuit. Based on formula (3) and formula (4), the kernel voltage td and t (SS) are 9.36 ms and 5.46 ms respectively, and the peripheral I/O voltage td and t (SS) they are 24 ms and 14 ms respectively. Connect the PWRGD pin of the TPS54310 that generates kernel voltage to the SS/ENA pin so that, even if the capacitor breaks down, the output of the TPS54310 that generates kernel voltage does not reach the threshold value at the start of power-on, PWRGD outputs low levels, and the TPS54310 that generates peripheral I/O voltage is off until the kernel voltage is stable. This ensures that the kernel is powered on first: When power is down, the output of the TPS54310 generating kernel voltage is lower than the threshold, and the output of the PWRGD pin is low, and the output of the TPS54310 generating peripheral I/O voltage is turned off, ensure that the peripheral I/O is powered off first.

3. voltage monitoring and reset circuit
In the design of Radar Video Signal Simulator, due to the high-frequency characteristics of the video card circuit, both the electromagnetic radiation of the switch and the line noise will interfere with the working voltage of the circuit device. In addition, DSP and FPGA have high requirements on the operating voltage, and the deviation cannot exceed 5%. Once the operating voltage exceeds this deviation, it is easy to shorten the lifetime of the device or even burn the device for a long time.
Destroy. Therefore, the system design needs to monitor the operating voltage of the device in real time through the voltage monitoring circuit to ensure that the system provides stable and normal voltage.
Working principle of the voltage monitoring circuit: the reset signal of the monitoring device is valid during power-on, so that the DSP and other devices are always in the reset state, once all the monitored voltage values reach the specified threshold voltage, the reset and DSP devices can be released to work normally. During operation, if any monitoring voltage falls below the threshold, the monitoring device sends a reset signal again to reset the system.
The voltage monitoring and reset circuit is implemented by TPS3307-18D of TI Company. TPS3307-18D is a microprocessor power controller that can simultaneously output high and low effective reset signal; at the same time monitor three independent voltage: 3.3 V, 1.8 V, adjustable voltage; with an Internal timer, after reset, even if the monitoring voltage has been
If the threshold is exceeded, the system still needs 200 ms to exit the reset state. This ensures that the system completes initialization during the reset period. The reset signal of DSP, FPGA and other devices in this system is effective at low level. Therefore, the reset signal of TPS3307-18D is adopted, and reset is used as the reset indication, implement voltage monitoring of 3.3 V, 1.8 V, 1.2 V (amplified to 3.6 V) in the system, as shown in voltage monitoring and reset circuit 4. As long as the power supply voltage of the TPS3307-18D is higher than 1.1 V, when any voltage in the monitored voltage is lower than its threshold value, a reset signal can be issued to reset the relevant device. In addition, the TpS3307-18D also has a manual reset signal, which is manually reset by the reset button.

4 PCB layout and peripheral device Selection
Because the switch DC-DC has high frequency interference, so in the PCB layout and peripheral device selection should pay attention to reasonable wiring and selection of appropriate peripheral devices, can effectively reduce the switch noise. Note that the position of the output capacitor should be close to the output end of the inductor: The Power Inductor wiring should be as wide as possible, and the feedback input end of the error amplifier should be far away from the power inductor. In order to make the tps54310 work normally under a large load, it is necessary to ground the Heat pad in a large area to speed up heat dissipation. However, the peripheral components should choose the Power Inductor with a shielding cover and the output capacitor with low esr.

5 conclusion
It has been proved that the power system designed by the system can provide stable power for Radar Video simulators, at the same time, the conversion rate is as high as 92%, the output voltage ripple is less than 0.05 V, the output power is up to 19 W, and the dynamic response is fast. In addition, the voltage monitoring and reset circuit enables the entire system to work stably for a long time, while also avoiding DSP loading exceptions caused by voltage fluctuations, therefore, the power system designed in this system is also applicable to other DSP systems.