/Proc/cpuinfo

ARCH/ARM/include/ASM/cputype. h

ARCH/ARM/kernel/setup. c

1. read_cpuid_id (cpuid_id)

# Define read_cpuid (REG )\
({\
Unsigned int _ Val ;\
ASM ("MRC P15, 0, % 0, C0, C0," _ stringify (REG )\
: "= R" (_ Val )\
:\
: "Cc ");\
_ Val ;\
})

Read midr registers

# Define arm_cpu_part_cortex_a9 0xc090
# Define arm_cpu_part_cortex_a5 0xc050
# Define arm_cpu_part_cortex_a15 0xc0f0
# Define arm_cpu_part_cortex_a7 0xc070
# Define arm_cpu_part_cortex_a12 0xc0d0

CAT/proc/cpuinfo

Processor: armv7 processor rev 1 (v7l)
Processor: 0
Model name: armv7 processor rev 1 (v7l)
Bogomips: 48.00
Features: SWP half thumb fastmult vfp edsp neon vfpv3 TLS vfpv4 idiva idivt vfpd32 evtstrm
CPU Implementer: 0x41
CPU architecture: 7
CPU variant: 0x0
CPU part: 0xc0d
CPU revision: 1


Processor: 1
Model name: armv7 processor rev 1 (v7l)
Bogomips: 48.00
Features: SWP half thumb fastmult vfp edsp neon vfpv3 TLS vfpv4 idiva idivt vfpd32 evtstrm
CPU Implementer: 0x41
CPU architecture: 7
CPU variant: 0x0
CPU part: 0xc0d
CPU revision: 1


Processor: 2
Model name: armv7 processor rev 1 (v7l)
Bogomips: 48.00
Features: SWP half thumb fastmult vfp edsp neon vfpv3 TLS vfpv4 idiva idivt vfpd32 evtstrm
CPU Implementer: 0x41
CPU architecture: 7
CPU variant: 0x0
CPU part: 0xc0d
CPU revision: 1


Hardware: Something (flattened Device Tree)
Revision: 0000 (implemented at the board level and can be stored in CPLD, gpio control, Flash, etc)
Serial: 0000000000000000 (board-level implementation is acceptable, and OMAP is used to mark the die ID)