Push-pull output and open-drain output

The following describes the structure of the open-drain output and push-pull output:

Push-Pull output: Can output high, low level, connect digital devices;

Open-Drain output: The output is equivalent to a transistor collector. A pull-up resistor is required to obtain a high level state. Suitable for the current-type drive, its ability to absorb current is relatively strong (generally 20ma or less).
Push-pull structure is generally referred to as two transistors by two complementary signal control, always in one transistor on the time of the other cutoff.
To achieve "line and" need to use OC (open collector) gate circuit. Is two parameters of the same transistor or MOSFET, in the push-pull mode exists in the circuit, each responsible for positive and negative half-week waveform amplification task. When the circuit is working, two symmetrical power switch tubes have only one conduction at a time, so the conduction loss is small and the efficiency is high. The output can either sink current to the load or pump current from the load.

Characteristics and application of open-drain circuit


In circuit design we often encounter the concept of open drain (open collector) and open set (open).
The "leak" referred to in the concept of the open-drain circuit refers to the drain of the MOSFET. Similarly, the "set" in the open collector Circuit refers to the collector of the transistor. The open-drain circuit refers to a circuit with a very high output of the MOSFET leakage. The general usage is to add a pull-up resistor to the circuit outside the drain. The complete open-drain circuit should consist of an open-drain device and an open-drain pull-up resistor. 1 is shown below:

The circuit forming the open-drain form has the following characteristics:
1. Take advantage of the drive capability of the external circuit to reduce the internal drive (or drive the load higher than the chip supply voltage). When the IC internal MOSFET is on, the drive current is from the external VCC through R pull-up, MOSFET to GND. Only a very lower gate drive current is required inside the IC. 1.

2. You can connect multiple open-drain pins to a single line. form a relationship of "and logic". 1, when Pin_a, Pin_b, pin_c any one lower, open the line logic is 0. This is also the principle of I2c,smbus bus to determine the state of bus occupancy. If the pull-up resistor must be connected as output. In the capacitive load, the falling delay is the transistor in the chip, the active drive, the speed is fast, the rising delay is the passive external resistor, the speed is slow. If the speed of high resistance is required to select small, power consumption will be large. Therefore, the choice of load resistance should take into account both power consumption and speed.
3. You can change the transmission level by changing the voltage of the pull-up power supply. 2, the logic level of the IC is determined by the power Vcc1, while the output high level is determined by the VCC2 (the power supply voltage of the pull-up resistor). This allows us to control the output logic with low level logic (so you can convert at any level). (for example, with a pull-up resistor, the Ttl/cmos level output can be provided.) )



4. The open-drain pin does not connect the external pull-up resistor, it can only output low (therefore, for the classic 51 single-chip P0 port, to do the input and output function must be added to the external pull-up resistor, otherwise the high-level logic can not be output). In general, the open-drain is used to connect different levels of the device, matching the level of the.
5. Standard open-drain feet generally have only the ability to output. Add other judgment circuit, can have bidirectional input, output ability.

6. The normal CMOS output stage is the upper and lower two tubes, remove the above pipe is open-drain. The main purpose of this output is two: level conversion, line and.

7. Line and function is mainly used in the case of multiple circuits to the same signal to pull low operation, if this circuit does not want to pull low, the output high level, because the open-drain above the pipe is taken off, high level is by the external pull-up resistor to achieve. (While the normal CMOS output stage, if one output is high and the other one is low, it is equal to the power supply short circuit.) ）

8.open-drain provides a flexible way to output, but it also has its weaknesses, which is the delay of the rising edge. Because the rising edge is the load charging through the external pull-up passive resistor, so when the resistance choice hour delay is small, but the power consumption is large, and the delay large power consumption is small. Therefore, if the delay is required, it is recommended to use a falling edge output.

The application should be noted that:
1. The principle of open-drain and open-set is similar, in many applications we use open collector circuit instead of open leakage path. For example, an input pin requirement is driven by an open-drain circuit. Our common driving method is to use a transistor to form an open-collector circuit to drive it, that is, convenient and cost-saving. 3.


2. The resistance of the pull-up resistor R pull-up determines the speed at which the logic level translation is along. The greater the resistance, the lower the power consumption. Vice versa.




Push-pull output is generally referred to as the push-pull output, in the CMOS circuit should be more appropriate than the CMOS output, because in the CMOS push-pull output capacity can not do the double pole so large. The output capability looks at the area of the IC's internal output pole N tube p tube. Compared with the open-drain output, the high and low level of the push-pull is determined by the IC's power supply, and cannot be simply done by logic operation. The Push-pull is now the most used output stage design in CMOS circuits.



Of course, open drain is not without cost, this is the output of the driving capacity is very poor. The poor driving power of the output is inaccurate, and the drive capability depends on the final transistor power in the IC. OD is only the delay of the rising edge, because the rising edge is through the external pull-up passive resistor to charge the load, when the resistance select the hour delay is small, but the power consumption is large, whereas the delay large power consumption is small. The OPEN drain provides a flexible output mode, but it also has a price, and it is recommended to use a falling edge if there is a requirement for delay.



The precondition of small resistance delay is that the principle of resistor selection should be within the allowable range of last stage transistor power dissipation, and experienced designers will not choose 1 ohm resistor as pull-up resistor when using logic chip. In the pulse of the rising edge of the power supply through the pull-up passive resistance to charge the load, it is apparent that the smaller the resistance rise time is shorter, in the pulse of the falling edge, in addition to the load through the active transistor discharge, the power supply through the pull-up resistor and conduction of the transistor to form the path, the problem is the chip power The resistance affects the rising edge and does not affect the falling edge. If you do not care about the rising edge in use, the pull-up resistor can select as large a point as possible to reduce the current to the ground path. If the rising edge time requirement is higher, the choice of resistance size should be based on the chip power consumption as reference.



I. What is OC, OD

Open collector Gate (open collector OC or open source OD)
The open-drain is the meaning of an open-drain output, equivalent to an open collector (open-collector) output, which is an open collector (OC) output in the TTL. Generally used for wire or wire, and also for current drive.
Open-drain is the MoS tube, the open-collector is for the bipolar tube, in terms of usage is not very different.



Two. What is line or logic with line and logic?

The logic function of "and" can be realized by direct interconnection of line and logic, i.e. two outputs (including more than two). In the bus transmission and other practical applications need a plurality of doors in parallel connection of the output terminal, and the general TTL gate output can not be directly connected to use, otherwise these gates of the output pipe between the low impedance of the formation of a large short-circuit current (sink current), and burn the device. On the hardware, the OC Gate or the Tri-State Gate (St Gate) can be used to achieve this. With the OC door to achieve the line and should be at the same time the output port should be added a pull-up resistor.
Three-state Gate (St Gate) is mainly used in multiple gate output shared data bus, in order to avoid multiple gate output simultaneously occupy the data bus, these door enable signal (EN) Only one is allowed to have a valid level (such as high level), because the output of the tri-State gate is a push-pull low-impedance output, and do not need to pull So the switching speed is faster than the OC door, and the three-state gate is used as the output buffer.




On a junction (line), a pull-up resistor is connected to the collector C or drain D of the power supply VCC or VDD and n NPN or NMOS transistors, the emitter E or source S of these transistors are connected to the ground, and as long as a transistor is saturated, the junction (line) is pulled to the ground level.
Because these transistors have a base injection current (NPN) or gate Plus high level (NMOS), the transistor is saturated, so the relationship of these bases or gates to this node (line) is either non-nor logic. If the node is followed by an inverter, it is the or or logic.

Note: Personal understanding: Line and, connect the pull-up resistor to the power supply. (~a) & (~b) =~ (A+b), by the formula easier to understand the origin of the line and this concept;

The use of a pull-down resistor and PNP or PMOS tube can be used to form a non-NAND logic, or to convert and/or logic with a negative logic relationship.

Note: line or, connect the pull-down resistor to ground. (~a) + (~b) =~ (AB);
These transistors are often the open collector OC or open source OD output of some logic circuits. This logic is often referred to as line and/or line or logic, when you see the OC or OD output of some chips connected together, and there is a pull-up resistor, which is the line or/line with the, but sometimes the pull-up resistor is done on the chip input. By the way, if the output of the OC or OD chip is not connected, the two-way outputs on bus buses are managed together and can only have one output, while the other is high impedance state can only be entered.




Three. What is a push-pull structure
Generally refers to two transistors are controlled by two complementary signals, always in one transistor on the time of the other cutoff. To achieve the line with the need to use OC (open collector) gate circuit. If the output stage has two transistors, always in a conduction, a cutoff state, That is, two three-stage pipe push-pull connected, such a circuit structure called push-pull circuit or totem pole (totem-pole) output circuit.



When the output is low, that is, the lower load gate input low, the output current will be the lower door into the T4; When the output is high, that is, the lower load gate input high, the output of the current will be subordinate door from the level of the power supply by T3, D1 pull out. In this way, the output high and low level, T3 and T4 Road will be alternating work, thereby reducing the power consumption, improve the capacity of each tube. And because no matter where to go, the resistance of the tube is very small, so that the RC constant is very small, the transition speed is very fast. Therefore, the push-pull output stage improves the load capacity of the circuit and improves the switching speed. For your reference.
Push-pull circuit is two parameters of the same transistor or MOSFET, to push-pull mode exists in the circuit, each responsible for positive and negative half-cycle of the waveform amplification task, the circuit works, two symmetrical power switch tube only one conduction at a time, so the conduction loss of small efficiency. The output can either sink the current to the load or pull the current from the load



Push-pull circuit is suitable for low voltage and high current, it is widely used in power amplifier circuit and switch supply.
Its advantages are: simple structure, high switching transformer core utilization, push-pull circuit work, two symmetrical power switch tube only one conduction at a time, so the conduction loss is small.
The disadvantage is: the transformer with a central tap, and the switch tube withstand voltage is high; Due to the existence of leakage sense of the original side of the transformer, the power switch-off moment, the drain source will produce a large voltage spike, and the input current ripple is larger, so the size of the input filter is larger.



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Some basic concepts

Latch: The state of the output does not change with the state of the input, only the state entered when there is a latched signal is saved to the output until the next latched signal. Typically there are only 0 and 12 values. A typical logic circuit is a D trigger.


Buffer: Multi-use on the bus, improve the driving capacity, isolation before and after the stage, the buffer is mostly three-state output function. A tri-state buffer is a typical line-and-logic device that allows multiple devices to be hung on a single bus, although the OC output can also be used on-line and logic applications.

Build time and hold time

　

Figure 1

Setup time is the time at which the data is stable until the clock signal rises along the trigger, and if the settling time is not enough, the data will not be hit on the rising edge of the clock, and the hold time is the arrival of the rising edge of the trigger's clock signal. Data is stable time, if the time is not enough, the data can not be driven into the trigger. 1.

Data stable transmission must meet the requirement of establishing and holding time, of course, in some cases, the value of settling time and hold time can be zero. PLD/FPGA development software can automatically calculate the setup and hold time of two related inputs (2)


Competition, adventure, Burr


Competition: In the combinational logic circuit, an input variable is transmitted to the output by two or more channels, and because of the delay time of each route, the time to reach the output gate comes first, and this phenomenon is called competition. The phenomenon of competition that does not produce false output is called non-critical competition. The competitive phenomenon that produces temporary or permanent error output is called critical competition.

Adventure: a phenomenon in which an unexpected signal occurs in a digital circuit at an instant. The "1" adventure is caused by the addition of a variable's original variable and the inverse variable to the gate input. The "0" adventure is caused by the addition of a variable's original variable and the inverse variable to either the input or the gate.


Discriminant method:

1 Algebraic method: In the expression of logical function, if a variable appears in both the original variable and the inverse variable, it has a competitive condition. Remove the other variables, leaving a competitive variable, if the expression is: f=a+/a, will produce "0" adventure, f=a*/a, will produce "1" adventure.

2 Karnaugh Map method: As long as there are two tangent but disjoint rings in the Carnot diagram (the "0" adventure is a 1-formed circle, the "1" Adventure is a circle of 0), it will create an adventure.


Elimination Method:

1 Modify the Design method: 1 Algebra method, in the creation of the logical expression of the phenomenon, plus redundant or multiply the redundancy factor, 2 Karnaugh map method, the Carnot diagram in the tangent of the ring with an extra circle connected together.

2 Selection method: In the circuit is added to the signal, after the output signal is stable, the selection allows output, resulting in the correct output.

Filtration method: Since the adventure Pulse is a very narrow pulse, one or two can be terminated with a hundreds of micro capacitor at the output to filter it out.

The dangerously of the combinational logic circuit only occurs at the moment when the signal state changes, the risk is transitional, it does not deviate the steady-state value from normal, but in the sequential circuit, the risk is essential, which can cause the output value of the circuit to deviate from normal or oscillate forever.
The Adventures of combinational logic circuits are transitional adventures, ranging from adventure waveforms to static adventures and dynamic adventures.
The steady-state value of the output is the same before and after the input signal changes, but when the input signal changes, the output signal produces a glitch, which is a static adventure. If the output steady state value is 0, there is a positive sharp pulse glitch, called static 0 dangerously. If the output steady state value is 1, there is a negative sharp pulse glitch, it is called static 1 adventure.
Before and after the input signal changes, the steady-state value of the output is different, and burr occurs at the edge, called Dynamic Dangerously (adventure).
From the specific causes of risk-taking, risk can be divided into functional adventures and logical adventures. function risk is inherent in the logic function itself, and when multiple input variables change, logical adventures often occur. The simplest way to avoid a function risk is to allow only a single input variable to change at the same time, or to take a sampling approach.
When a single input variable changes, a function adventure does not occur, but when the circuit is not designed properly, there is still a logical adventure. By carefully designing and modifying the structure of the circuit, logic adventures can be eliminated.

Reasons for internal burr production in PLD

When we use discrete components to design a digital system, because of the PCB traces, there are distributed inductance and capacitance, so a few nanoseconds of the burr will be naturally filtered, and in the PLD no distribution inductance and capacitance, so in the PLD/FPGA design, competition and risk problems will become more prominent.

Push-pull output and open-drain output