PWM Series 1

I. Conceptual understanding

The PWM input capture mode is a special case of the input capture mode, which is understood as follows

1. Each timer has four input capture channels IC1, IC2, IC3, IC4. and IC1 IC2 a group, IC3 IC4 a group. and the corresponding relationship between the PIN and the register is set.

2. The same tix input maps two ICX signals.

3. The two ICX signals are valid on opposite polarity edges, respectively.

4. One of the two edge signals is selected as the trigger signal, and the slave mode controller is set to reset mode.

5. When the trigger signal arrives, it is set to the capture register that triggers the input signal, capturing "a pwm period (i.e. a continuous two rising or falling edge)", which equals the Tim

The number of clock cycles (that is, the Count N of the Tim that is captured in the capture register).

6. Another capture channel captures a count m of the edge signal of the triggering signal and the next opposite polarity, i.e. (i.e., the period of high-level or low-level)

7. It is possible to calculate the clock period and duty cycle of the PWM

Frequency=f (Tim Clock frequency)/n.

Duty cycle= (High count N/a),

If M is a high-level count, then duty cycle=m/n

If M is a high-level count, then duty cycle= (N-M)/n

Note: Since the counter is 16 bits, the maximum number of cycles is 65,535, so the measured minimum frequency = Tim clock frequency/65535.

Second, the procedure design and analysis

1. Overview of the program: select TIM3 as the PWM input capture. The IC2 is set to the rising edge and is set to a valid trigger input signal. So the capture register of the IC2 captures the PWM period,

The capture register of the IC1 captures the high-level period of the PWM.

2. The program code is as follows:

/* TIM3 Clock Enable */
Rcc_apb1periphclockcmd (RCC_APB1PERIPH_TIM3, ENABLE); Clock configuration

/* GPIOA Clock Enable */
Rcc_apb2periphclockcmd (Rcc_apb2periph_gpioa, ENABLE);

/* TIM3 Channel 2 pin (pa.01) configuration */
Gpio_initstructure.gpio_pin = gpio_pin_7; Gpio Configuration
Pio_initstructure.gpio_mode = gpio_mode_in_floating;
Gpio_initstructure.gpio_speed = Gpio_speed_50mhz;

Gpio_init (Gpioa, &gpio_initstructure);

/* Enable the TIM3 global Interrupt */
Nvic_initstructure.nvic_irqchannel = TIM3_IRQN; Nvic Configuration
nvic_initstructure.nvic_irqchannelpreemptionpriority = 0;
nvic_initstructure.nvic_irqchannelsubpriority = 1;
Nvic_initstructure.nvic_irqchannelcmd = ENABLE;
Nvic_init (&nvic_initstructure);

/*tim Configuration */

Tim_icinitstructure.tim_channel = tim_channel_2; Channel selection
tim_icinitstructure.tim_icpolarity = tim_icpolarity_rising; Rising Edge Trigger
Tim_icinitstructure.tim_icselection = Tim_icselection_directti; Pin-to-register relationship
Tim_icinitstructure.tim_icprescaler = TIM_ICPSC_DIV1; Enter the Prescaler. Control how many input cycles to do once capture, if

The input signal frequency does not change and the measured period does not change. For example, select 4, then every four input cycles to do a capture, so that when the input signal changes infrequently,

Can reduce the number of times the software is constantly interrupted.
Tim_icinitstructure.tim_icfilter = 0x0; Filter setting, through several periodic jump to determine the waveform stability 0x0~0xf

Tim_pwmiconfig (TIM3, &tim_icinitstructure); Configuring the Tim peripheral information according to the parameters

/* Select the TIM3 Input TRIGGER:TI2FP2 */
Tim_selectinputtrigger (TIM3, TIM_TS_TI2FP2); Select IC2 to always trigger the source

/* Select the slave mode:reset Mode */
Tim_selectslavemode (TIM3, Tim_slavemode_reset);//tim from mode: rising edge of trigger signal reinitialize counter and trigger register update event

/* Enable the master/slave Mode * *
Tim_selectmasterslavemode (TIM3, tim_masterslavemode_enable); Passive triggering of the start timer

/* TIM Enable counter */
Tim_cmd (TIM3, ENABLE); Start TIM2

/* Enable the CC2 Interrupt Request * *
Tim_itconfig (TIM3, TIM_IT_CC2, ENABLE); Open interrupts

Interrupt handler function

void Tim3_irqhandler (void)
{
/* Clear TIM3 Capture Compare interrupt pending bit */
Tim_clearitpendingbit (TIM3, TIM_IT_CC2); Clear Tim's interrupt pending bit

/* Get the Input Capture value */
Ic2value = Tim_getcapture2 (TIM3); Reads the value of the IC2 capture register, which is the count value of the PWM period

if (Ic2value! = 0)
{
/* Duty Cycle computation */
Dutycycle = (Tim_getcapture1 (TIM3) * +)/ic2value; Reads the value of the IC1 capture register and calculates the duty ratio

/* Frequency computation */
Frequency = 72000000/ic2value; Calculates the PWM frequency.
}
Else
{
dutycycle = 0;
Frequency = 0;
}
}

Note (a): If you want to change the measured PWM frequency range, the TIM clock frequency can be divided processing

Tim_timebasestructure.tim_period = 0xFFFF; Cycle 0~FFFF
Tim_timebasestructure.tim_prescaler = 5; Clock frequency division, the number of 5+1 that is 6 divided
tim_timebasestructure.tim_clockdivision = 0; Clock segmentation
Tim_timebasestructure.tim_countermode = tim_countermode_up;//Mode
Tim_timebaseinit (TIM2, &tim_timebasestructure);//Basic initialization
Note (ii): Timer Tim's multiplier X1 or X2. When the APB divide is 1 o'clock, the multiplier value is 1, otherwise 2

PWM Series 1