Renesas Basic Learning----PWM output

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Pulse width modulation (PWM) is a method for digitally encoding analog signal levels. With the use of high-resolution counters, the duty ratio of the square wave is modulated to encode the level of a specific analog signal. The PWM signal is still digital, because at any given moment the full-amplitude DC power supply is either fully (on) or completely none (OFF). A voltage or current source is a repeating pulse sequence with a pass (on) or off (off) that is added to the analog load. When the DC power supply is added to the load, when the power supply is broken. Any analog value can be encoded using PWM as long as the bandwidth is sufficient.

On Renesas ' microcontroller, the system can be configured to output PWM waveforms via the configuration register. Table 6-1 in the data sheet is a good illustration of how to use the time Register of the r7f to make it output a PWM waveform.

PWM is configured so many registers are (only a few of the above table is not configured), because basically is the timer not only has PWM output also has the interval timer, the square wave output, the external event counter, the divider, the input pulse interval measurement, the input signal high/low level width measurement, the delay counter, Single-trigger pulse output, so configure the register to allow time to choose from a wide range of functions.

The first configuration of the PER0 in Tau0en is 1, allowing the input clock to be supplied. Then use the TPS0 to get the CK01, CK00 these two clocks (in the choice of channel 0 and Channel 1 is the clock can choose a clock as two clock, of course, can also be a Channel One clock). The next step is to control the timer unit start-Stop TE0, TS0, TT0, wherein the data sheet TE0 is described in detail.

That means we don't have to configure it here.

The TS0 and TSH0 registers are trigger registers that initialize the Timer/counter register 0n (tcr0n) and start counting operations on each channel. Enable The TT0 and TTH0 registers are trigger registers for counting operations that stop each channel. (inactive)

Next is the control output register TOE0, TO0, TOL0, TOM0, where the TOE0 register is used to allow or disallow timer output from each channel. The TO0 register is the buffer register for each channel's timer output. The TOL0 register is a register for controlling the output level of each channel timer. The TOM0 register is used to control the timer output mode for each channel. (Here we choose TOM0 's TOM01 as 1: Slave channel output mode)

Here are Tmr0xh and TMR0XL. The tmr0n register includes two 8-bit registers for setting the operating mode of channel N. This register is used to select the working Clock (FMCK), select the Count clock, select Primary/secondary, select either 16-bit or 8-bit timers (Channel 1 only), set start trigger and capture trigger, select the effective edge of the timer input, and set the operating mode (interval, capture, event counter, single count, or capture & Single count).

The last is tdr0xh and TDR0XL, where both the initial value and the empty ratio are set. During a continuous read or continuous write operation, if you insert a write operation to Tdr0nh, read to TDR0NL, or read to tcr0n, the data for the read operation and the write operation will not be guaranteed.