(Reporter) de2 (SOC) (de2)

Abstract
The most troublesome part of de2 is the SDRAM, but its large capacity has to be used. below is where I know the official information of Altera is sent to the SDRAM.

Introduction
The following are some of the documents I have found that the Altera official website has discussed SDRAM.

1. de2 original ephemeral CD
\ De2_tutorials \ tut_de2_sdram_1_logstores
\ De2_tutorials \ tut_de2_sdram_vhdlals

2. Quartus II handbook volumn 4: FPGA Builder
Ch.8 building memory subsystems using SDRAM builder in version 7.2 Is p.8-14

3. Quartus II handbook volumn 5: Embedded peripherals
Ch.1 SDRAM controller core

See also
(Formerly known as "4 port") how to use hardware to access SDRAM (4 port) in de2 )? (IC design) (de2)
(Original) how to access SDRAM with hardware in de2? (IC design) (de2)
(Original release) How can I access the SDRAM with the receiver in de2? (IC design) (de2) (nio ii)