SDRAM Detailed Introduction

Concept Introduction:

sdram:synchronous dynamic random Access memory, which is synchronized with the RAM. Synchronization refers to its clock frequency and the CPU front-end bus system clock is the same, and the internal command of the transmission and data transfer are based on it, dynamic refers to the storage array needs to constantly refresh to ensure that the data is not lost, random refers to the data is not linear storage, but the freedom to specify the address to read and write data.

Internal structure of SDRAM memory chip
1. Logic Bank and chip bit width:
Now for an in-depth understanding of the internal structure of SDRAM. The main concept here is the logical bank. Simply put, the inside of the SDRAM is a storage array. Because if it's piped storage, it's hard to do random access.

The array, like a table, "fills in" the data, and you can think of it as a form. As with the table's retrieval principle, specify a row (row), and then specify a column (columns), we can accurately find the desired cell, which is the basic principle of memory chip addressing. For memory, this cell is called a storage unit, so what is this table called? It is the logical Bank (referred to as L-bank). The following figure is a diagram of a storage array (L-bank).

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Due to technical, cost and other reasons, it is impossible to do only a full-capacity l-bank, and most importantly, due to the operating principle of SDRAM, single L-bank will cause very serious addressing conflicts, greatly reduce memory efficiency. So people in the SDRAM internal division into a number of L-bank, earlier than two, is currently 4, which is the maximum number of L-bank in the SDRAM specification.

In this way, it is necessary to determine the l-bank before addressing, and then select the corresponding row and column in the selected L-bank. Visible access to memory can only work one l-bank at a time, and each time the data exchanged with the memory controller is the capacity of a "storage unit" in the L-bank storage array. In some vendors ' representations, the storage unit in L-bank is called word.

and SDRAM memory chip transmission of data is the chip's bit width, then the capacity of this storage unit is the chip's bit width, but mainly, this relationship is only valid for SDRAM. The reasons are explained in the following article.

Tip: How dram is stored

The storage unit in the L-bank is the underlying storage unit, its capacity is several bits (for SDRAM, the chip's bit width), and each bit is stored in a separate storage. These are the smallest storage units in memory. You can use the relationship between the cluster and the sector in the hard disk operation to understand the storage in memory form. A sector is the smallest storage unit on a hard disk, and each cluster contains more than one sector, and the exchange of data is done in a single cluster (the data of one storage unit is transmitted at a time).

DRAM storage schematic diagram: The line selection and the selection of signals will enable the storage capacitance and the transmission circuit between the outside, so as to discharge (read) and charge (write). In addition, the image of the flash amplifier design is not fixed, the current function is incorporated into the readout amplifier, the specific operation described in detail below.

2. Storage capacity of the chip:
Now we should clear the basic organizational structure of the memory chip. So how to calculate the capacity of memory. Obviously, the capacity of the memory chip is the sum of the capacity of all the storage units in the L-bank. The method for calculating how many storage units and the number of units in a table is calculated is the same:
Number of storage units = number of rows * Number of columns * L-bank

In many memory product introduction documents, the capacity of the chip is expressed in m*w way. M is the total number of storage units in the chip, the unit is trillion (should be write m), W represents the capacity of each storage unit, that is, the SDRAM chip bit width (width), the unit is bit. The calculated chip capacity is also in bits, but the user can be converted to bytes (byte) by dividing by 8. 8m*8, for example, is a 8bit-bit wide chip with 8M storage units and a total capacity of 64Mbit (8MB).

Pin and package for 3.SDRAM:

The memory chip wants to work, must have the connection with the memory controller, at the same time for an electrical component, the power supply is also essential, and the data transmission must have a clock as the trigger reference. Therefore, the SDRAM will be in the package to set aside the corresponding PIN for use. The power and clock pins don't have to say much, and now we can imagine at least those control pins.

We have a basic understanding of the steps of memory addressing, from which we can understand the general situation of memory work. It should be explained here that SDRAM has its own industry design specifications, in a capacity standard, SDRAM pin/signal standard can not only consider a bit width of the design, but to take into account a variety of bit width, and then try to give a common standard, small bit wide chip also line out some pins, But the high-width chips may be all used. But the capacity is not the same, the design standards will be different, the smaller the general capacity of the chip requires less pins.

Pin and package for 3.SDRAM:

The memory chip wants to work, must have the connection with the memory controller, at the same time for an electrical component, the power supply is also essential, and the data transmission must have a clock as the trigger reference. Therefore, the SDRAM will be in the package to set aside the corresponding PIN for use. The power and clock pins don't have to say much, and now we can imagine at least those control pins.

We have a basic understanding of the steps of memory addressing, from which we can understand the general situation of memory work. It should be explained here that SDRAM has its own industry design specifications, in a capacity standard, SDRAM pin/signal standard can not only consider a bit width of the design, but to take into account a variety of bit width, and then try to give a common standard, small bit wide chip also line out some pins, But the high-width chips may be all used. But the capacity is not the same, the design standards will be different, the smaller the general capacity of the chip requires less pins.

(1) First, we know that the memory controller must determine a chip before addressing the chip. So there is a chip selection signal, which is used to select the chip. The selected chip will receive or read the data, so there is a chip selection signal.

(2) next to the selected chip for the same L-bank addressing, the current SDRAM in the number of L-bank up to 4, so to two L-bank address signal.

(3) The last is the same row/column addressing of the selected chip. The number of address lines should be designed separately according to the structure of the chip. But at the same capacity, the number of rows is the same, and only the number of columns varies depending on the bit width, the larger the bit width, the less the number of columns because the required storage units are reduced.

(4) After finding the storage unit, the selected chip will be unified data transmission, then must have the same number of bits and width of the same amount of data I/O channels, so there must be a corresponding number of data line pins.

Now we basically know some of the memory chip signal pin, the figure below is a simple SDRAM diagram, you can see in detail.

Figure Note: Pin graphs with different bit widths for 128Mbit chips (NC is not used,-indicates the same as the interior bit width design).

PIN definitions are shown in the following table:

Pin code	Defined
Vdd/vddq	Operating/DQ Voltage
Vss/vssq	Grounding of the corresponding voltage
d/qn	Data I/O lines
An	Row and column address lines
DQM	Data mask
cs#	Chip selection
cas#	Column Address strobe pulse
ras#	Line Address Strobe pulse
Ck	Clock signal
CKE	Clock valid
BAn	L-bank Address Line
we#	Write permission

Internal basic operation and working sequence of 4.SDRAM:

We have already learned the basic signal lines used by SDRAM, below to see how they are "arranged" inside the SDRAM chip, and from here to understand the basic operation and process of memory, in this section we will be exposed to the heavenly book called the sequence diagram, but do not be afraid, according to the guidance of the text slowly understand , you can definitely read it. First of all, we first know about the internal structure of SDRAM, and then begin to describe it in detail.

128Mbit (32MX4) SDRAM internal structure diagram

(1) Initialization of the chip:

Many people may not imagine that there is a logic control unit inside the SDRAM chip, and there is a pattern register for it to provide control parameters. Therefore, each time you turn on the SDRAM must first initialize this control logic core. The implications for pre-charging and refreshing are described below. The critical phase is in the setup with the mode register (the model register), referred to as Mrs. This work is performed by the memory controller, and the information for the Register is provided by the address line.

The initialization process of SDRAM at boot time

The operation parameters controlled by the SDRAM mode register: The address line provides different 0/1 signals to obtain different parameters. After the setup to Mr, it starts to enter the normal working state, the relevant parameters in the diagram will be described in detail below.

(2) The line is valid:

After initialization is complete, to address an array in a L-bank, first determine the row (row), make it Active (active), and then determine the column. Although they were previously addressed in the film and L-bank, they are valid at the same time as the row.

Line Effective time series diagram

As can be seen from the figure, at the same time, cs#, L-bank addressing, RAS (row address Strobe, line addresses strobe pulse) is also in a valid state. At this point an address line sends a specific line address, so a total of 4,096 rows, the different values of A0-A11 determine the specific line address. Because the row is valid and the corresponding L-bank is valid, the line is valid and can also be called L-bank valid.

(3) column reading and writing:

Once the row address has been determined, the address of the column will be addressed. However, the address line is still the A0-A11 used for the line address. Yes, in SDRAM, the line address is shared with the column address line. However, how is the read/write command issued? In fact, no signal is sent to read or write the explicit command, but through the chip's writable state control to achieve the purpose of reading/writing. Obviously the we# signal is a key. When the we# signal is invalid, of course it is the Read command.

SDRAM basic Operation command, through a combination of various control/address signals (h for high level, l for low level, x indicates that there is no effect on the low-voltage average). In this table, all commands, except the self-refresh command, are default Cke valid. For self-refresh commands, the following are detailed.

Both the column addressing signal and the read-write command are issued simultaneously. Although address lines are shared with row addressing, CAS signals can differentiate between open and column addressing, with A0-A9,A11 to determine specific column addresses.

Read and write operation schematic, the reading command and the column address a piece issued (when the we# is low is the Write command).

However, there must be an interval between the Send column read and write command and the line valid command, which is defined as TRCD, which is RAS to CAS delay (RAS-to-CAS latency), which can be understood as a row-by-pass cycle, which should be a delay based on the response time of the chip storage array electronics. TRCD is an important timing parameter for SDRAM, which can be adjusted by setting the SOC's memory controller, but not exceeding the manufacturer's predetermined range. The generalized trcd, in terms of the number of ticks, such as trcd=2, represents a delay period of two clock cycles, depending on the clock frequency, to the exact time.

(4) Data output (read)

After the selected column address, the specific storage unit has been identified, and the rest is that the data is output to the memory bus via the data I/O channel. However, after the CAS is issued, it still takes a certain amount of time to have the data output, from the time the CAs and the read commands are emitted to the first data output, are defined as CL (CAS latency,cas incubation period). CL is also known as the read latency because CL is only present when it is read. CL units, like TRCD, are the number of clock cycles, which are time-consuming and clock-frequency-specific.

However, CAS does not reach the storage unit after the CL cycle. In fact, CAS and RAS are just as instantaneous, but CAS have a faster response time. Why is it. Assuming that the bit width of the chip is n bit, the number of columns is C, then a row address to select the N*c storage, and a column address just select N storage. However, the reflection time of the transistor in the storage body still causes the data not to be triggered on the same rising edge as the CAS, and must delay at least one clock cycle.

Because of the chip volume, the capacitance in the storage unit is very small, so the signal must be amplified to ensure its effective identification, the amplification/drive work by S-amp, a storage body corresponding to a s-amp channel. But it has to have a preparation time to ensure the signal transmission intensity, so from the data I/O bus has a data output before the rising edge of the clock, the data has been transmitted to the s-amp, that is, the data has been triggered, after a certain driving time finally transmitted to the data I/O bus output, This time we call it the TAC (access time from CLK, which is accessed after the clock is triggered). The unit of the TAC is NS, which has different explicit rules for different frequencies, but must be less than one clock cycle, otherwise the efficiency will be reduced due to too long access time. It should be emphasized that each data is read with a TAC, including in sequential reads, only the TAC that begins the second data while the first data is being transmitted.

CL can not exceed the design specifications of the chip, otherwise it will cause the memory instability, settings will not boot, and it can not be temporarily changed before the data read. The CL cycle is set in the Mrs Stage of the boot initialization too long.

However, as can be seen from the structure diagram of the storage body, the original logic state of 1 capacitor after the read operation, the discharge will be converted into logic 0. Therefore, the previous DRAM ensures the reliability of the data in order to close the current row. To rewrite the information in the storage body, this task is done by the refresh amplifier that the data passes through, it rewrites the data according to the logic level state, because this operation and the output of the data are synchronous complementary conflicts, so there is no new rewrite delay. Later through the improvement of technology, the refresh amplifier is canceled, its function is replaced by S-amp, because it will maintain the logical state of the data when read, play a role of the cache, read again by it directly sent, different in the new addressing output, the data re-operation can be completed in the pre-charging phase.

(5) data input (write)

The data write operation is also done after TRCD, but there is no CL at this time (remember that CL only appears in the read operation), the line addressing and column addressing sequence diagram and the same as above, only when the column addressing, we# is a valid state.

Timing diagram for Data writes

As can be seen from the figure, because the data signal is emitted by the control side, the input chip does not need to do any tuning, just directly into the data input register, and then by the write drive to the storage capacitor charging operation, so the data may be sent simultaneously with the CAs, that is, the write delay is 0. However, the data is not written in a timely manner to the storage capacitance, because the transistor and capacitor charging must have a period of time, so the actual data write needs a certain period. To ensure reliable data writes, sufficient write/calibrate times (Twr,write Recovery time) are set aside, and this operation is also known as writeback. TWR at least one clock cycle or more, the impact on it is described further below.

(6) Burst length

Burst (Burst) refers to the continuous transmission of the contiguous storage unit in the same row, the number of storage units involved in a continuous transfer is the burst length. At present, because the memory controller once read/write a location-wide data, that is, 8 bytes, but in reality, less than 8 bytes of data is rarely seen, so generally have to go through multiple cycles of data transmission. The read/write operation described above is addressed to a single storage unit at a time, and if you want to read/write continuously, the next cell of the current storage unit is addressed, that is, to continuously send the column address and read and write commands. Although the same read/write latency allows data transmission to be continuous on the I/O side, it consumes a large amount of memory control resources and is inefficient when data is continuously transmitted without the ability to enter new commands. To this end, people have developed a burst transmission technology, only specify the starting address and burst length, the memory will automatically in turn to the corresponding number of storage units behind the read/write operation, no longer need the controller to provide the column address continuously. Thus, in addition to the first data transmission requires a number of cycles, then each data is only one cycle to obtain.

Non-burst continuous read mode: Instead of burst transmission, it is addressed separately in sequence, which can be equivalent to bl=1. Although you can make the data continuous transmission, but each time to send the column address and command information, control resource consumption is very large.

As for the value of BL, it is also not allowed to be randomly determined before the data is transmitted. BL is set during the Mrs phase of the initialization process described above. The currently available options are 1, 2, 4, 8, and full page; The common setting is 4 or 8. By the way, the change in BL can be very much related to the design of the memory controller and may not be supported.

In addition, in the Mrs Stage in addition to set the BL value, but also to determine the mode of read/write operation and burst transmission mode. Burst read/Burst write, indicating that the read and write operations are burst transmission, each read/write operation only the length of the BL set, which is the general setting. Burst read/single write, indicating that the read operation is burst transmission, write operation is only a separate. The burst mode represents the transmission sequence of the storage units involved in the burst cycle. Sequential transfer refers to the sequential reading from the starting cell. If bl=4, the starting unit number is N, the order is n+1, n+2, n+3. Interleaved transmission is to disrupt the normal sequence of data transmission (such as the first transmission unit is N, and the second transmission unit is n+2 instead of n+1), as for the interleaving rules in the SDRAM specification has a detailed definition table, but in this case, the necessity and length of consideration is not listed.

7. Pre-charge

Since SDRAM's addressing is exclusive, after the read and write operation, if another line of the same l-bank is to be addressed, it is necessary to close the original valid row and resend the row/column address. L-bank the existing work line is closed, the action to prepare to open the new line is pre-charge (Precharge). The pre-charge can be controlled by the command, or the chip can be automatically pre-charged after each read and write operation via the auxiliary setting. In fact, pre-charging is a data rewrite for all the storage in the work line and resets the line address while releasing the S-amp (re-adding the comparator voltage, typically 1/2 of the capacitance voltage, to help determine the logic level of the read data, Because the S-amp is determined by a reference voltage compared to the stored position line voltage, the logic values are judged to prepare the work of the new line. Specifically, the data in the S-amp is written back. Even the non-working storage will be disturbed by the s-amp of the storage capacitance, so it needs to be rewritten after reading. At this point, the capacitance of the power will be the basis for judging the logic state, to set a critical value, usually 1/2 of the capacitance, more than its logic 1, to rewrite; otherwise, logic 0 does not rewrite. For this reason, it is now essential to connect the other end of the capacitor to a specified voltage, rather than grounding it to help with the comparison and judgment of the override.

Now we look back at the command sequence diagram of the read and write operation, where we can find that the address line A10 controls whether or not the current L-bank automatically pre-charge after reading and writing, which is the "auxiliary setting" mentioned above. In a separate pre-charge command, the A10 controls whether the specified L-bank or all L-bank are pre-charged, and the former needs to provide the L-bank address, which only requires the A10 signal to be placed high.

After a pre-charge command is issued, it takes a while to allow a valid command to send a RAS line to open a new work line, which is called TRP (Precharge command Period, pre-charge order cycle). As with TRCD, CL, the unit of TRP is also the clock cycle, the specific value depends on the clock frequency.

Pre-charge timing diagram on read: cl=2,bl=4,trp=2. The start time for automatic pre-charging is the same as this diagram, except that there is no separate pre-charge command, and when the Read command is issued, the A10 address line is set to high (allowing automatic pre-charging). It is important to control the pre-charge start-up time, which can enter the address of the new line immediately after the read operation, guaranteeing efficiency.

8. Refresh
It is called DRAM because it is constantly refreshed (refresh) to hold data, so it is the most important operation for DRAM. The refresh operation, like the one rewritten in the pre-charge, is read-and-write first with S-amp. But why is there a pre-charge operation to be refreshed? Because pre-charging is a work-line operation on one or all of the l-bank and is irregular, the refresh has a fixed period, which in turn operates on all rows to preserve the data in the memory that has not been rewritten for a long time. However, unlike all l-bank pre-charging, the rows here refer to the same rows in all L-bank, while the work-line addresses in each l-bank in the pre-charge are not necessarily the same.

So how often do you repeat a refresh? The current accepted standard is that the storage capacitance of the data effective shelf life limit is 64ms, that is, each row refresh cycle is 64ms, so the refresh speed is: The number of rows/64ms. When we look at the memory specifications, we often see the 4096 refresh Cycles/64ms or 8192 refresh cycles/64ms, where 4096 and 8192 represent the number of rows per L-bank in the chip. The refresh command is valid for one row at a time, and the send interval varies with the total number of rows, which is 7.8125us when the 15.625us,8192 line is 4096 rows.

There are two types of refresh operations: Automatic refresh (auto refresh, or AR) and self refresh (auto refresh, referred to as SR). Regardless of the Refresh method, you do not need to provide the row address information externally, because this is an internal automatic operation. There is a line address generator (also known as a row refresh counter) inside the ar,sdram that is used to automatically generate the row address sequentially. Because the refresh is for all the storage in a row, no column addressing is required, or CAS is valid before RAS. Therefore, AR is also known as CBR-style refresh. Since the refresh involves all L-bank, all l-bank stop working during the refresh process, and each refresh takes up to 9 clock cycles, which can then enter a normal working state, meaning that all work orders can only wait for the 9 clock cycles to execute. After 64ms, the same row is refreshed again, so the cycle is refreshed. Obviously, the refresh operation will certainly have an impact on the performance of SDRAM, but this is no way to do things, but also the cost of DRAM compared to SRAM costs advantages of pay at the same time.

SR is mainly used in the sleep mode low-power state of data preservation, the most famous application is str. When the AR command is issued, the CKE is placed in an invalid state, and it enters the SR mode, where it is no longer dependent on the system clock, but is refreshed based on the internal clock. All external signals are not valid except Cke during SR, and only re-cke valid to exit from refresh mode and enter normal operation state.

9. Data mask

We talked about the burst length when we were talking about read/write operations. If bl=4, then that means the 4*64bit data is transmitted at one time. However, what to do if the second data is not needed. Can you still transfer it. In order to block unwanted data, people have adopted a data mask (DQM) technology. With DQM, memory can control which output or input data the I/O port cancels. What needs to be stressed here is. It should be emphasized that when reading data, the masked data will still be removed from the storage, but masked at the "Mask Logical Unit". The DQM is controlled by the memory controller.

SDRAM Official Rules, DQM issued two clock cycles after the read, and at the time of writing, DQM and write commands are effective immediately.

When the data mask operation is read, the DQM takes effect after two cycles, and the second data of the burst period is canceled.

When the data mask operation is written, the DQM takes effect immediately, and the second data of the burst period is canceled.

The basic operation of the internal memory to this end, in fact, there are a lot of memory operation is not described, but are not very important, limited to the length and necessity, we do not introduce, interested readers can see the relevant information on their own.

Note: The content of this article is copied from the Master Advanced _ Ultimate Memory Technology Guide. If in doubt, please leave a message to discuss. It is highly recommended to read.