Simulation of I2C bus multi-master communication research and Software Design

Simulation of I2C bus multi-master communication research and Software Design

Author:■ Zheng Xuyang, Xi'an University of electronic science and technology, Li Bingbing, Huang Xinping

Abstract:This paper introduces the principle of multi-master communication simulating I2C bus, and proposes a new implementation method. This method uses delayed receiving comparison to implement arbitration, so that common Microcontroller (MCU) without I2C interfaces can implement multi-master communication that simulates I2C bus, at the same time, it has played a positive role in the promotion of I2C bus.

Keywords:Multi-master communication using analog I2C bus

The I2C bus (Inter IC Bus) is a two-way two-line serial communication standard launched by Philips. It has been widely used due to its few interfaces and high communication efficiency ~ 3/]. In addition to simple single-master communication, it can also be applied to multi-master communication systems. In a multi-master communication system, if two or more Master nodes start data transmission at the same time, the bus has the conflict detection and arbitration functions to ensure normal communication and prevent data destruction. Many Microcontroller (MCU) now have I2C bus interfaces, which can facilitate I2C bus design. For MCU without I2C bus interface, two I/O interface lines can be used for simulation/[2, 3/]. At present, some materials about simulation of I2C are mainly about communication in a single master node system, which makes the application of simulation of I2C bus have certain limitations. Based on the idea of bus arbitration, this paper proposes a multi-master node communication idea and implementation process.

1 I2C bus system Introduction [1 ~ 3]

The I2C bus system is composed of two buses, namely, the SCL (serial clock) and SDA (serial data. This bus has strict timing requirements. When the bus is working, the serial clock line (ASR) transmits the clock pulse and the serial data line (SDA) transmits the data. The bus protocol specifies that each master node must have a start, end, send data, and response signal for communication. These signals are basic units in the communication process. Each frame of data transmitted by the bus is 1 byte. Each time one byte is sent, the receiving node sends a response signal accordingly. The Protocol stipulates that the 1st-byte high 7-bit address after the bus is started is the addressing address of the slave node, the 8th bits are the direction bits ("0" indicates the write operation performed by the master node on the slave node; "1" indicates the read operation performed by the master node on the slave node), and the remaining bytes are the operation data. Figure 1 lists the timing of several basic signals on the I2C bus.

Figure 1 shows the start signal, stop signal, response signal, non-response signal, and the time sequence of transmitting data "0" and Data "1. The initial signal is the SDA line from high to low when the SCL line is high; the stop signal is the SDA line from low to high when the SCL line is high; the SDA is low when the answer signal is high, and the SDA is high when the non-response signal is high. The transmitted data "0" and Data "1" are the same as the send response bit and non-response bit time sequence diagrams.

Figure 2 shows a complete data transfer process. After the I2C bus sends the start signal, the 7-bit addressing address and 1-bit of the slave machine indicate the read/write bit of the operation. After the response signal is received, the data is transmitted until the stop signal is sent. Data is in bytes. Each time the sending node sends one byte, it must check whether the SDA line has received a response signal. If yes, it will continue sending; otherwise, it will stop sending data.

2 I2C bus arbitration

In a multi-master communication system. There are multiple nodes on the bus, all of which have their own addressing addresses and can be accessed as slave nodes by other nodes, both of them can send control bytes and transmit data to other nodes as the master node. However, if two or more nodes send start signals to the bus and start to transmit data, a conflict arises. To resolve such conflicts, arbitration decisions must be made. This is the arbitration on the I2C bus.

　　　　　　　　

Arbitration on the I2C bus is divided into two parts: the synchronization of the SCL line and the arbitration of the SDA line. Because the bus has the logic function of line "and", that is, as long as one node sends low power, the bus performs low. When all nodes send high power, the bus can be displayed as high. It is precisely because of the principle of the line "and" logic function that when multiple nodes send clock signals at the same time, the bus displays a unified clock signal. This is the synchronization principle of the SCL.

The SDA line arbitration is also based on the principle that the bus has the line "and" logic function. After a node sends one-bit data, it compares the data presented on the bus with the data sent by itself. Yes, continue sending; otherwise, withdraw from competition. Figure 3 shows the arbitration process of two nodes on the bus. SDA-line arbitration ensures that the communication works normally when multiple master nodes attempt to control the bus at the same time and data is not lost. The bus system allows only one master node to continue occupying the bus [1] through arbitration.

Figure 3 uses two nodes as an example of the arbitration process. Data1 and data2 are the data signals sent by the master node to the bus. SDA is the data signal presented on the bus, and the SCL is the clock signal presented on the bus. When both master nodes 1 and 2 send the start signal at the same time, both master nodes send the High-level signal. At this time, the signal displayed on the bus is high. Both master nodes detect that the signal on the bus is the same as the signal sent by themselves, and continue to send data. At 2nd clock cycles, both master nodes send low-level signals, and the signals displayed on the bus are low-level signals. Data continues to be sent. In 3rd clock cycles, master node 1 sends high-level signals, while master node 2 sends low-level signals. According to the logic function of the bus line "and", the signal on the bus is low. At this time, master node 1 detects that the data on the bus is different from the data sent by itself, the data output level is disconnected and switched to the receiving status from the slave machine. In this way, master node 2 won the bus, and the data is not lost, that is, the bus data is the same as the data sent by master node 2, while master node 1 continues to receive data after it is switched to slave node, similarly, the SDA online data is not lost. Therefore, no data is lost during the arbitration process.
　　　　　　　　
Figure 3 arbitration process of two master nodes

3 principle and implementation process of multi-master communication

Multi-master communication means that there are multiple nodes on the bus. These nodes can be used as the master node to access other nodes, or as the slave node to be accessed by other nodes. When multiple nodes attempt to occupy the bus at the same time, the bus arbitration is required. It is now difficult to study how to implement bus arbitration to simulate I2C bus systems. Document/[4/] proposes to add a busy line to the system to check whether the busy line is occupied before occupying the bus. If the bus is idle, set the busy line and transmit data to the bus. Otherwise, the bus is not occupied until the bus is idle. This method has two disadvantages: ① the biggest advantage of I2C is that there are few interfaces and high efficiency. This not only increases the use of resources but also reduces the advantages of I2C bus; ② when the number of master nodes is large, the wait time is long and the efficiency is not high. Based on the principle of bus arbitration, this design proposes a arbitration Method Based on latency comparison. When the master node wants to occupy the bus, it first checks whether the bus is idle. If the bus is idle, it sends data. When sending data, the data on the bus is received and compared with the sent data. If they are different, it means that there are other nodes on the bus, so they exit; otherwise, they will end until the data is sent. This method not only reflects the efficiency of I2C bus, but also has good scalability.
　　　　　　　　　　　　　　
Figure 4 Multi-master communication process

Figure 4 shows the multi-master communication process based on latency comparison. The process of MCU as the slave node is shown in Figure 5. Before the node sends the start signal, check whether the bus is idle (whether busy is 0 ). The detection method used here is to continuously check whether the level on the bus is always high for a period of time. If it indicates that the bus is idle, otherwise it indicates that other nodes are using the bus, wait for a while before sending. When the bus is idle, it sends the start signal and the slave Node Address byte to be accessed. Each sent data is received once to check whether the sent data is consistent with the received data. If yes, the data continues. Otherwise, the data jumps out of the receiving status of the slave node. If there is no conflict, the MCU continues to send data as the master node until the task ends, and then sends the stop signal and returns. If the data is different, the MCU will jump to the slave node status. The data in the accumulators (ACC) and work registers (RI) does not change during the jump to the receiving status of the slave node, so the data is not lost, as a slave node, you can continue to receive data on the bus. In this way, the entire communication process is not interrupted, and data is not lost.
　　　　　　　　　　　　　　
Figure 5 process from Node

Figure 5 shows the slave node process. When entering the slave node, you must set busy to high. This indicates that the MCU is currently working and cannot complete other tasks. After the MCU completes the receiving task as a slave node, set busy to low. After receiving the addressing byte, the MCU compares it with its own address byte. If you access your accesskey, you can access the following receiving program. Otherwise, the program jumps out. When you access yourself, you also need to determine whether the master node reads or writes data to enter the corresponding program. In the subprogram of writing bytes, check whether there is a response signal (ACK) after each 1-byte data is sent from the node. If yes, the data is received. Otherwise, jump out of the waiting state, resend. In the subprograms of reading bytes, each time one byte of data is received, one response signal (ACK) is sent to show that the reception is normal. Otherwise, the master node will stop sending messages. In the existing documents, the principle and source code of the slave node are relatively small. Here we provide the source code for writing the byte subroutine as the slave node. Due to limited space, other subprograms are not listed.

4-part source code

This section describes some source code in MCU multi-master communication. There are several difficulties and key points in the implementation of multi-master communication. First, when writing a byte subroutine as the master node, it should include each data sent and the data of the bus for comparison and judgment. If the data is different, jump out and enter the slave node status. Since only the Pc value is changed when the subroutine returns the main program, the values in the accumulators (ACC) and work registers (RI) remain unchanged, therefore, after the MCU enters the slave state, it continues to receive the remaining data of the bus, so that the data of the bus is not lost. Second, it is used as a child program for writing bytes from the slave node. Since the clock line is controlled by the MCU of the master node, it is difficult to read the SDA line data based on the SCL line. The third is the determination of the slave node with a subaddress on whether to write bytes or read segments. When writing a node, the master node sends a new starting signal and sends the address data from the node again. In this case, you need to determine whether to read or write data from the node and enter the corresponding subroutine. The source code of the above three key and difficult subprograms is provided for your reference. These source codes have been proven to be correct.

The write-byte subroutine of the master node:
The NOP can be added or subtracted Based on the clock speed.
Wrbyte: mov r0, #08 h
CLR busy; clears the busy Value
WLP: rlc a; Data bit
JC wr1
Sjmp wr0; Determine the data bit
Wlp1: djnz r0, WLP
NOP
Out1: Ret
Wr1: setb sda; send 1
NOP
SETB SCL
MoV C, SDA; Determine whether it is the same as the sent data
JC goon
SETB busy
Ajmp out1
Goon: NOP
NOP
NOP
CLR SCL
Sjmp wlp1
Wr0: clr sda; send 0
NOP
SCL
NOP
NOP
NOP
NOP
NOP
CLR
SCL
Sjmp wlp1
Write byte subroutine from the node (returned as ACK ):
Swrbyte: mov r0, #08 h
Wagain: RRC
MoV B, #37 h
Wwait1: JB check, wwait1; wait until the check mark is low.
JC wr1; Determine whether to send "1" or "0"
Setb sda; send "1"
Ajmp com
Wr1: clr sda; send "0"
COM: djnz r0, wwait2; Determine whether the message has been sent
Wwait3: jnb scl, wwait3; after sending, wait for the response signal
Wwait4: jb scl, wwait4
Wwait5: jnb scl, wwait5
CLR ACK
Jb sda, st0
SETB ACK
St0: ret; Return
Wwait2: JNB check, wwait2; wait until the check mark is high.
Sjmp wagain
A subroutine used to determine whether a start signal exists while reading bytes from a node. If there is a start signal, it is converted into a byte Subroutine:
Srdbyte: mov r0, #08 h
SETB 20 h; set the flag to determine whether to read or write
Setb sda; release Bus
Rwaitj: JNB check, rwaitj; wait until the check mark is high
MoV C, SDA; read data from the bus
Rrc a; Accumulators
Dec R0
MoV C, acc.7; Determine whether it is the starting signal
JNC rwaitj1; Continue reading data for low
Rewait: jnb scl, rwaitj1; start to judge whether it is the starting signal
Jb sda, rewait
CLR 20 h; yes, the flag is cleared and return
Ajmp sjrdout
Rwaitj1: JB check, rwaitj1; wait until the check mark is low
Rwaitj3: JNB check, rwaitj3; wait until the check mark is high
MoV C, SDA
RRC
Djnz r0, rwaitj2
Sjrdout: Ret
Rwaitj2: jb scl, rwaitj2; Continue to read data when the SCL is low
Sjmp rwaitj3

5. Summary

Based on the arbitration principle in the bus protocol, the proposed method of simulating I2C multi-master communication based on latency comparison not only reflects the efficiency of I2C bus, but also has good scalability. It enables common MCU with no I2C interface to be applied in Multi-master communication systems. It not only increases the application scope of common MCU, but also breaks through the Application limitations of analog I2C bus, it has played a positive role in promoting I2C bus.

References

1 The i2cbus specification, Version 2.1. January, 2000. http://www.philips.com
2 Zhang Kun, Qiu Yang, Liu Hao. Design of I2C bus in CPLD-based system. Application of electronic technology, 2003 (11)
3 He Limin. Design of I2C bus application system. Beijing: Beijing University of Aeronautics and Astronautics Press, 1995
4 Zhang Dongmei, Fan Shibin, He Weimin. General Software Package for simulating I2C bus multi-master communication. Application of Single Chip Microcomputer and embedded system, 2003 (12)

Zheng Xuyang, Li Bingbing, and Huang Xinping: Master's degree student. He focuses on digital communication and communication systems.