SPI bus protocol Introduction

SPI bus protocol Introduction 1. Technical Performance
The SPI interface is the serial peripheral interface first proposed by Motorola for full duplex three-line synchronization. It adopts the master-slave mode architecture and supports multi-Slave Mode Applications. Generally, it only supports single master. The clock is controlled by the master. In the case of a shift pulse, data is transmitted in bit. The high position is in front and the low position is in the back (MSB first). The SPI interface has two unidirectional data lines for full duplex communication, currently, the data rate in applications can reach several Mbps. Shows the bus structure.

Ii. Interface Definition
The SPI interface has four signal lines: Device Selection Line, clock line, Serial Output data line, and serial input data line.
(1) MoSi: data output from the main device
(2) miso: master device data input, output from device data
(3) sclk: clock signal generated by the main device
(4)/SS: Enabling signal from the device, controlled by the main device
Iii. Internal Structure
Iv. Clock polarity and Clock Phase
In the SPI operation, the two most important settings are clock polarity (cpol or ucckpl) and clock phase (cpha or ucckph ). The clock polarity sets the level when the clock is idle. The Clock Phase sets the clock edge for reading data and sending data.
The data sent by the host and slave are completed at the same time, and the received data is also completed at the same time. Therefore, in order to ensure correct communication between the master and slave machines, the SPI should have the same clock polarity and clock phase.

SPI interface clock configuration experience: When configuring the SPI interface clock on the master device side, you must understand the clock requirements of the slave device, because the clock polarity and phase on the master device side are based on the slave device. Therefore, in the clock polarity configuration, you must determine whether the device receives data from the rising or falling edge of the clock, whether the data is output from the falling edge of the clock or the rising edge.

V. Transmission Time Series
The internal hardware of the SPI interface is actually two simple shift registers. The transmitted data is 8 bits, which are transmitted by bit under the enable signal and shift pulse generated by the master device, the highest is in front, and the lowest is in the back. As shown in, when the data changes on the descent edge of sclk, a data on the rising edge is stored in the shift register.
V. Data Transmission
During an SPI clock cycle, the following operations are performed:
1) The host sends 1-bit data through the MoSi line, and the slave machine reads the 1-bit data through the line;
2) The slave sends one-bit data through the miso line, and the Host reads the data through the line.
This is achieved through shift registers. As shown in, each host and slave have a shift register, which is connected to a ring. With the clock pulse, data is removed from the host register and slave register in sequence from the high to the low, and in turn to the slave register and host register. When all the content in the register is removed, it is equivalent to completing the exchange of the two register content.

Vi. Advantages and Disadvantages

The SPI interface has the following advantages:

1) supports full-duplex operations;

2) Easy to operate;

3) high data transmission rate.

It also has the following Disadvantages:

1) it needs to occupy a large number of port lines of the host (each slave needs a line selection );

2) Only one host is supported.

3) There is no specified traffic control and no response mechanism to confirm whether data is received.