SPI debugging for dm355

For dm355evm
There is no SPI device in the/dev folder, and there is only one EEPROM device. This device is controlled using the SPI interface. The device file of the device is/dev/mtdblock5. the driver is at25xxa_eeprom.c. Why is his device file/dev/mtdblock5? In the eeprom_probe function of at25xxa_eeprom.c
Ret = add_mtd_device (MTD) adds the eeprom to the mtdblock linked list. The source code is as follows:

Run debug (0, "MTD: giving out device % d to % s \ n", I,
MTD-> name); The following is printed:
Drivers/SPI. cmtd: giving out Device 5 to spi_eeprom

We can also see that.
MTD: giving out device 0 to bootloader
MTD: giving out device 1 to Params
MTD: giving out device 2 to Kernel
MTD: giving out device 3 to filesystem1
MTD: giving out Device 4 to filesystem2

If you do not need the EEPROM, you can modify the driver to the SPI driver.
The main underlying driver files include four SPI. c SPI. h dm355_spi_master.h dm355_spi_master.c
SPI. C and SPI. h are mainly used to encapsulate the upper layer dm355_spi_master.h of the SPI driver.
Dm355_spi_master.c accesses the underlying register.

At the beginning of the debugging, we found a bug. When sending n Bytes, there will always be more than one number.
In addition, CS has a small glitch before the last number is sent.
Read the code later
I found that the last byte was intentionally added by the author.
To prevent this glitch from affecting access to the eeprom control data.
I checked the underlying SPI register of dm355 and found that the problem lies in the spidat1 register.
I went to the Internet to find the solution and found the dm355 error table. It turned out to be a chip bug!
Modify the SPI according to the solution on the error table
Calling SPI write continuous write count (or SPI read reading) c s is always enabled.
However, there is a section in the middle of the CS before reading the data first.
The result of the speed test is:
The spi clk is 4 MHz
The SPI read/write speed is 300000 Bytes/s.
In Linux, the interface functions for separate access of registers by byte can be found in include» ASM-arm» arch-DaVinci.
In Io. h

00001 /*
00002 * DaVinci Io address definitions
00003 *
00004 * copied from include/ASM/ARM/arch-OMAP/IO. h
00005 *
00006*2007 (c) montavista software, Inc. This file is licensed under
00007 * The terms of the GNU General Public License version 2. This program
00008 * is licensed "as is" without any warranty of any kind, whether
Express
00009 * or implied.
00010 */
00011 # ifndef _ asm_arch_io_h
00012 # DEFINE _ asm_arch_io_h
00013
00014 # define io_space_limit 0 xffffffff
00015
00016 /*
00017 *
----------------------------------------------------------------------------
00018 * I/O Mapping
00019 *
----------------------------------------------------------------------------
00020 */
00021 # define io_phys 0x01c00000
00022 # define io_offset 0xfd000000/* virtual IO = 0xfec00000 */
00023 # define io_size 0x00400000
00024 # define io_virt (io_phys + io_offset)
00025 # define io_p2v (PA) + io_offset)
00026 # define io_v2p (VA)-io_offset)
00027 # define io_address (x) io_p2v (X)
00028
00029 /*
00030 * We don't actually have real ISA nor PCI buses, but there is so secure
00031 * drivers out there that might just work if we fake them...
00032 */
00033 # define pcio_base 0
00034 # DEFINE _ IO (A) (void _ iomem *) (pcio_base + ()))
00035 # DEFINE _ mem_pci ()
00036 # DEFINE _ mem_isa ()
00037
00038 # ifndef _ javaser __
00039
00040 /*
00041 * functions to access the DaVinci Io Region
00042 *
00043 * Note:-use davinci_read/write [BWL] for physical register addresses
00044 *-use _ raw_read/write [BWL] () for virtual register addresses
00045 *-use io_address (phys_addr) to convert registers to virtual
Addresses
00046 *-do not use hardcoded virtual addresses to allow changing
The
00047 * IO address space again if needed
00048 */
00049 # define davinci_readb (A) (* (volatile unsigned char
*) Io_address ())
00050 # define davinci_readw (A) (* (volatile unsigned short
*) Io_address ())
00051 # define davinci_readl (A) (* (volatile unsigned int
*) Io_address ())
00052
00053 # define davinci_writeb (V, A) (* (volatile unsigned char
*) Io_address (A) = (V ))
00054 # define davinci_writew (V, A) (* (volatile unsigned short
*) Io_address (A) = (V ))
00055 # define davinci_writel (V, A) (* (volatile unsigned int
*) Io_address (A) = (V ))
00056
00057/* 16 bit uses ldrh/strh, base +/-offset_8 */
00058 typedef struct {volatile 2010offset [256];} _ regbase16;
00059 # DEFINE _ regv16 (vaddr) (_ regbase16 *) (vaddr )&~ 0xff ))\
00060-> offset [(vaddr) & 0xff)> 1]
00061 # DEFINE _ reg16 (paddr) _ regv16 (io_p2v (paddr ))
00062
00063/* 8/32 bit uses LDR/STR, base +/-offset_12 */
00064 typedef struct {volatile u8 offset [4096]; }__ regbase8;
00065 # DEFINE _ regv8 (vaddr) (_ regbase8 *) (vaddr )&~ 4095 ))\
00066-> offset [(vaddr) & 4095)> 0]
00067 # DEFINE _ reg8 (paddr) _ regv8 (io_p2v (paddr ))
00068
00069 typedef struct {volatile u32 offset [4096]; }__ regbase32;
00070 # DEFINE _ regv32 (vaddr) (_ regbase32 *) (vaddr )&~ 4095 ))\
00071-> offset [(vaddr) & 4095)> 2]
00072
00073 # DEFINE _ reg (paddr) _ regv32 (io_p2v (paddr ))
00074 # else
00075
00076 # DEFINE _ reg (x) (* (volatile unsigned long *) io_p2v (X )))
00077
00078