SPI Bus Summary

The abbreviation for the Serial Peripheral Interface (Serial peripheral interface,spi). is a high-speed, full-duplex, synchronous communication bus that occupies only four wires on the chip's pins. Motorola is first defined on its MC68HCXX series processors. The SPI interface is used primarily in eeprom,flash, real-time clocks, ad converters, and digital signal processors and digital signal decoders.

The SPI communication principle is very simple, it works in the master-slave mode, which usually has a master device and one or more slave devices, requires at least 4 wires, in fact 3 can also (unidirectional transmission). It is also common to all SPI-based devices, which are SDI (data input), SDO (data output), SCLK (clock), CS (chip Select).

(1) sdo– main equipment data output, from the device data input;

(2) sdi– main equipment data input, from the device data output;

(3) sclk– clock signal, generated by the main equipment;

(4) cs– from the device to enable the signal, controlled by the main device.

Where CS is the control chip is selected, that is, only the chip selection signal is pre-defined enabling signal (high potential or low potential), the operation of this chip is effective. Therefore, multiple SPI devices are allowed to be connected on the same bus. The CS signal is sometimes also a ss_n, and the ss_n signal is useful from the device to identify the new packet.

The data is output through an SDO line, where the data changes at the rising or falling edge of the clock, and is read immediately after the falling or rising edge. Complete a data transfer, and the input uses the same principle. In this way, the transfer of 8 bits of data can be done at least 8 times when the clock signal is changed (the top and bottom edges are one time). Disadvantages of the SPI interface: There is no flow control specified, and there is no response mechanism to confirm receipt of the data. The SPI bus works in four ways, the most widely used of which are the SPI0 and SPI3 modes.

The SPI interface in the internal hardware is actually two simple shift registers, the transmitted data is 8 bits, the main device generated from the device enable signal and the shift pulse, the bitwise transmission, high position in front, low post. Data changes on the falling edge of the SCLK, while a data is stored in a shift register.

The SPI bus has four modes of operation, the SPI module for data exchange with the peripheral, according to the peripheral operating requirements, its output serial synchronization clock polarity and phase can be configured, clock polarity (CPOL) has no significant impact on the transport protocol. If cpol=0, the idle state of the serial sync clock is low, and if cpol=1, the idle state of the serial sync clock is high. The clock phase (CPHA) can be configured to select one of two different transport protocols for data transfer. If cpha=0, the data is sampled on the first hop edge (up or down) of the serial sync clock, and if cpha=1, the second hop edge (up or down) of the serial synchronization clock is sampled. The SPI Master module and the external device that communicates with the clock phase and polarity should be consistent.

When configuring the SPI interface clock on this side of the main device, be sure to figure out the clock requirements from the device, since the clock polarity and phase on this side of the main device are based on the device. So in the configuration of the clock polarity it is important to figure out whether the device is receiving data on the rising or falling edge of the clock, whether the clock is falling along or rising along the output data. It should be noted, however, that since the SDO of the master device is connected from the SDI of the device, the SDO from the device connects the SDI of the main device, the data received from the device SDI is sent by the SDO of the master device, and the data received by the master device SDI is sent from the device SDO. So the configuration of the SPI clock polarity on this side of the main device (that is, the SDO configuration) is opposite to the polarity of the device's SDI receive data, which is the same polarity as the device SDO sends the data.

Note:

The 1 SPI signal is sometimes referred to as the MISO,SPI bus host input/slave output (SPI bus master input/slave Output), MOSI (master Output/slave input), Sclk,ss_n.

The 2 SPI protocol differs greatly from implementation.

Reference documents:

SPI (Serial peripheral Interface) Serial Peripheral Interface protocol detailed + instance.

http://my.oschina.net/freeblues/blog/67400

Serial peripheral Interface Bus. Https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus

SPI Bus Summary