Stm32 Flash read/write [library function]

Stm32 's built-in programmable flash is of great importance in many situations. such as its support for the ICP feature allows developers to Stm32 can be alerted to debug the development, can be through the JTAG and SWD interface to the STM32 program to write, support for the IAP feature allows developers to run the program at the time of the stm32 of their internal programs to update operations. For some requirements for data security, programmable Flash can be combined with stm32 internal unique identity to achieve a variety of anti-cracking solutions. and Stm32 Flash has a foothold in some lightweight anti-power storage solutions.  The flash of Stm32 is the main storage block and information block. The primary storage block is used to hold the specific program code and user data, and the information block is used to store the user configuration information area of the 2KB Boot program (Bootloader) and 512B from the Stm32 factory.  The primary storage block is divided into pages, with a page size of 1KB. The range is within 128KB beginning with address 0x08000000.  write operation to Flash to "erase first write" principle;Stm32 's built-in flash programming operations are written in pages, and the operation must be written in 16-bit half-width data bit units, allowing cross-page writes, and writing non-16-bit data will cause stm32 internal bus errors. the internal RC oscillator must be turned on when the built-in flash reads and writes.

#include "stm32f10x.h"
#include "stdio.h"

#define PRINTF_ON 1

void rcc_configuration (void);
void gpio_configuration (void);
void usart_configuration (void);

U32 count=0;

U16 data[5]={0x0001,0x0002,0x0003,0x0004,0x0005};

int main (void)
{
Rcc_configuration ();
Gpio_configuration ();
Usart_configuration ();

Rcc_hsicmd (ENABLE);

Flash_unlock ();

Flash_clearflag (flash_flag_eop| flash_flag_pgerr| FLASH_FLAG_WRPRTERR);

Flash_erasepage (0x8002000);

while (Count < 5)
{
Flash_programhalfword ((0x8002000 +count*2), Data[count]); Flash for a byte storage, 16-bit data must address plus 2

count++;

}

Flash_lock ();

Count = 0;

printf ("\ r \ n The Five Data is: \ r \ n");

while (Count < 5)
{

printf ("\ r%d \ r", * (U8 *) (0x8002000 + count*2)); Read method

count++;

}

while (1);

}

void Gpio_configuration (void)
{
Gpio_inittypedef gpio_initstructure;

Gpio_initstructure.gpio_speed = Gpio_speed_50mhz;

   gpio_initstructure.gpio_pin = gpio_pin_9;
   gpio_initstructure.gpio_mode = gpio_mode_af_pp;   
   gpio_init (Gpioa, &gpio_initstructure);  
&NBSP;
   gpio_ Initstructure.gpio_pin = gpio_pin_10;
   gpio_initstructure.gpio_mode = gpio_mode_in_floating;    
   gpio_init (Gpioa, &gpio_initstructure); 

void Rcc_configuration (void)
{
/* Define enum type variable Hsestartupstatus */
ErrorStatus Hsestartupstatus;

/ * Reset system Clock Settings * /
rcc_deinit ();
/ * Open hse*/
Rcc_hseconfig (rcc_hse_on);
/ * Wait for HSE to start vibrating and stabilize * /
hsestartupstatus = Rcc_waitforhsestartup ();
/* To determine if the HSE is successful, then enter if () inside * *
if (hsestartupstatus = = SUCCESS)
   {
/* Select HCLK (AHB) clock source for SYSCLK 1 */
Rcc_hclkconfig (RCC_SYSCLK_DIV1);
/* Select PCLK2 Clock source for HCLK (AHB) 1 */
Rcc_pclk2config (RCC_HCLK_DIV1);
/* Select PCLK1 Clock source for HCLK (AHB) 2 */
Rcc_pclk1config (RCC_HCLK_DIV2);
/ * Set Flash delay period of 2 * /
flash_setlatency (flash_latency_2);
/ * Enable Flash prefetch cache * /
Flash_prefetchbuffercmd (flash_prefetchbuffer_enable);
/* Select Phase-locked loop (PLL) clock source for HSE 1, double frequency 9, the PLL output frequency is 8MHz * 9 = 72MHz */
rcc_pllconfig (RCC_PLLSOURCE_HSE_DIV1, rcc_pllmul_9);
/ * Enable PLL * /
Rcc_pllcmd (ENABLE);
/ * Wait for the PLL output to stabilize * /
while (rcc_getflagstatus (rcc_flag_pllrdy) = = RESET);
/ * Select SYSCLK Clock source for PLL * /
Rcc_sysclkconfig (RCC_SYSCLKSOURCE_PLLCLK);
/ * Wait for PLL to become SYSCLK clock source * /
while (Rcc_getsysclksource ()! = 0x08);
   } 
/ * Open the Gpioa clock on the APB2 bus * /
Rcc_apb2periphclockcmd (rcc_apb2periph_gpioa| Rcc_apb2periph_usart1, ENABLE);

Rcc_ahbperiphclockcmd (RCC_AHBPERIPH_DMA1, ENABLE);

Rcc_apb1periphclockcmd (rcc_apb1periph_pwr,enable);
Rcc_apb1periphclockcmd (rcc_apb1periph_pwr| rcc_apb1periph_bkp| RCC_APB1PERIPH_WWDG, ENABLE);

}

void Usart_configuration (void)
{
Usart_inittypedef usart_initstructure;
Usart_clockinittypedef usart_clockinitstructure;

usart_clockinitstructure.usart_clock = usart_clock_disable;
Usart_clockinitstructure.usart_cpol = Usart_cpol_low;
 usart_clockinitstructure.usart_cpha = usart_cpha_2edge;                                                                                                                                                               
usart_clockinitstructure.usart_lastbit = usart_lastbit_disable;
Usart_clockinit (USART1, &usart_clockinitstructure);

Usart_initstructure.usart_baudrate = 9600;
Usart_initstructure.usart_wordlength = usart_wordlength_8b;
Usart_initstructure.usart_stopbits = Usart_stopbits_1;
usart_initstructure.usart_parity = Usart_parity_no;
Usart_initstructure.usart_hardwareflowcontrol = Usart_hardwareflowcontrol_none;
Usart_initstructure.usart_mode = usart_mode_rx| Usart_mode_tx;
Usart_init (usart1,&usart_initstructure);

Usart_cmd (usart1,enable);
}

#if printf_on

int FPUTC (int ch,file *f)
{
Usart_senddata (USART1, (U8) ch);
while (Usart_getflagstatus (USART1,USART_FLAG_TC) = = RESET);
return ch;
}

#endif

Stm32 Flash read/write [library function]