Tcl's read files for synthesis

The following file is to read all design files into Syntehsis tool automatically, like Cadence RTL Compiler.

1 SetSrcbasic ${hdlpath}/01_vhdlbasiclib2 SetSrcasictop ${hdlpath}/02_asic/01_top3 SetSrcrfid ${hdlpath}/02_asic/02_rfid4 SetSrcmsp ${hdlpath}/02_asic/03_msp4305 SetSrcperiph ${hdlpath}/02_asic/04_periph6 SetSrcopenmsp ${srcmsp}/openmsp430/Core/Rtl/Verilog7 8 9Set_attribute Hdl_search_path"${srcmsp}/include"Ten  One # filelists A SetFilelistbasiclib" -     ... ... - $srcbasic/pkg_types.vhd the $srcbasic/ffd.vhd -     ... ... - " -  + SetFilelistcommon" -     ... ... + $srcasictop/pkg_infil.vhd A $srcasictop/xfabmem_ent.vhd at     ... ... - " -  - SetfileList15693" - $srcrfid/iso15693/pkg_iso15693cmd.vhd - $srcrfid/iso15693/rx15693sym.vhd in     ... ... - " to SetfileList14443" + $srcrfid/iso14443/pkg_iso14443cmd.vhd - $srcrfid/iso14443/rx14443byte.vhd the     ... ... * " $ Panax Notoginseng SetFilelistrfid" -     ... ... the $srcrfid/fifo.vhd +     ... ... A " the  + SetFilelistopenmspxfab" - $srcmsp/omsp_and_gate.vhd $ $srcmsp/omsp_clock_gate.vhd $ " -  - SetFilelistopenmsp" the     ... ... - $srcopenmsp/omsp_clock_mux.vWuyi $srcopenmsp/omsp_clock_module.v the     ... ... - " Wu  - SetFilelistperiph" About $srcmsp/gpio/msp_io.vhd $     ... ... - " -  - SetFilelistmsp" A     ... ... + $srcmsp/msp430asic.vhd the " -  $ SetFilelisttop" the     ... ... the $srcasictop/infil.vhd the " the  -READ_HDL-VHDL ${filelistbasiclib}-Library Edclib inREAD_HDL-VHDL ${filelistcommon} theREAD_HDL-VHDL ${filelist15693} theREAD_HDL-VHDL ${filelist14443} AboutREAD_HDL-VHDL ${filelistrfid} theREAD_HDL-VHDL ${filelistopenmspxfab} theREAD_HDL-v2001 ${filelistopenmsp} theREAD_HDL-VHDL ${filelistperiph} +READ_HDL-VHDL ${filelistmsp} -READ_HDL-VHDL ${filelisttop}

Tcl's read files for synthesis