UART Receive FIFO and Receive Timeout

Why does UART need FIFO?

Modern CPUs run faster and faster. UART usually has a baud rate of less than 10 M. In the absence of FIFO, CPU time is consumed for each data filling to or from UART, this is a great waste. Therefore, the UART is configured with FIFO as the buffer for data sending and receiving on the hardware. Each time the CPU needs to fill in the data, it will fill in the uart tx fifo. Each time the CPU needs to get the data, the data will be retrieved from the uart rx fifo. In short, the existence of FIFO as a buffer reduces the CPU burden.

What is RX's data processing after FIFO?

Generally, when the rx fifo receives data that reaches the trigger level set by the rx fifo, an interruption is generated to the CPU, and the CPU enters the interrupt handler function to fetch the data. In this case, if the data transmitted once is not an integer multiple of the rx fifo trigger level, the final part of the data will not reach the rx fifo trigger level, what should I do? Can I retrieve this part of the RX FIFO data?

The following two methods are considered:

1. Set the rx fifo trigger level to 1, so that each time the rx fifo receives a data, an interruption will be triggered. It is impossible to have the rx fifo data trigger level insufficient, therefore, as long as there is data in the rx fifo, the CPU can know and process the data accordingly. But is there a big difference between this and no FIFO? Very small, CPU load is too heavy, and every time a piece of data is received, there will be an interruption.

2. Set the RX timeout interrupt to enable the interrupt, and set a timeout value to determine the time since the last time the data was received, the RX timeout interruption occurs.

At present, our company's uart rx timeout interrupt should have some problems. After enabling the timeout interrupt, when the UART does not receive any data, it still produces this timeout interrupt at a certain time, this is not normal.

# date && cat /proc/interruptsFri Jan  2 04:20:52 UTC 1970           CPU0        0:       1680  SIRFINTC  sirfsoc_timer0  6:          3  SIRFINTC  SGX ISR  8:          0  SIRFINTC  prima2-dsp 10:          1  SIRFINTC  ci13xxx_sirf 11:          0  SIRFINTC  ci13xxx_sirf 12:          0  SIRFINTC  sirfsoc_dma 13:         35  SIRFINTC  sirfsoc_dma 14:          0  SIRFINTC  sirfsoc-vip 18:      22799  SIRFINTC  sirfsoc-uart 24:         26  SIRFINTC  b00e0000.i2c 25:         13  SIRFINTC  b00f0000.i2c 30:      28322  SIRFINTC  SIRFSOC-FB 32:          0  SIRFINTC  sirfsoc_pwrc_int 33:          0  SIRFINTC  sirfsoc_tsc 34:          0  SIRFINTC  sirfsoc_adc 38:       8035  SIRFINTC  mmc0, mmc1 39:         52  SIRFINTC  mmc2, mmc3 52:          0  SIRFINTC  sysrtc.11128:          0  sirf-gpio-irq  ft5x0x_ts129:          0  sirf-gpio-irq  extcon-gpioIPI0:          0  CPU wakeup interruptsIPI1:          0  Timer broadcast interruptsIPI2:          0  Rescheduling interruptsIPI3:          0  Function call interruptsIPI4:          0  Single function call interruptsIPI5:          0  CPU stop interruptsIPI6:          0  CPU backtraceErr:          0# date && cat /proc/interruptsFri Jan  2 04:21:46 UTC 1970           CPU0        0:       1729  SIRFINTC  sirfsoc_timer0  6:          3  SIRFINTC  SGX ISR  8:          0  SIRFINTC  prima2-dsp 10:          1  SIRFINTC  ci13xxx_sirf 11:          0  SIRFINTC  ci13xxx_sirf 12:          0  SIRFINTC  sirfsoc_dma 13:         35  SIRFINTC  sirfsoc_dma 14:          0  SIRFINTC  sirfsoc-vip 18:      25674  SIRFINTC  sirfsoc-uart 24:         26  SIRFINTC  b00e0000.i2c 25:         13  SIRFINTC  b00f0000.i2c 30:      31779  SIRFINTC  SIRFSOC-FB 32:          0  SIRFINTC  sirfsoc_pwrc_int 33:          0  SIRFINTC  sirfsoc_tsc 34:          0  SIRFINTC  sirfsoc_adc 38:       8085  SIRFINTC  mmc0, mmc1 39:         52  SIRFINTC  mmc2, mmc3 52:          0  SIRFINTC  sysrtc.11128:          0  sirf-gpio-irq  ft5x0x_ts129:          0  sirf-gpio-irq  extcon-gpioIPI0:          0  CPU wakeup interruptsIPI1:          0  Timer broadcast interruptsIPI2:          0  Rescheduling interruptsIPI3:          0  Function call interruptsIPI4:          0  Single function call interruptsIPI5:          0  CPU stop interruptsIPI6:          0  CPU backtraceErr:          0

It can be seen that it generated more than 2000 interruptions in one minute, which is not normal.

Through investigation and study, we found that:

1. When will RX timeout be interrupted?

• Enable RX tiemout interruption and set the timeout value
• The rx fifo data is not empty, and new data is not received within the specified time period. The rx fifo data is not read empty during the specified time period, which causes the RX timeout interruption.

2. When to clear the interrupt?

• Go to the interrupt processing function and clear the interrupt.
• In the interrupt processing function, the rx fifo data is retrieved to null.

Therefore, by setting the RX timeout interrupt and the RX threshold interrupt, you can effectively cope with data acceptance in the IO mode.

• Use threshold to interrupt Data Handling
• Use timeout to interrupt Data Handling