UART register Introduction

Uartn_br: UART baud rate register
Uartn_br []: The content is regularly loaded by the timer's register.
Uartn_cr.run = 0 can be loaded until uartn_cr.run = 1 write is invalid

Uartn_txbufr: UART Transfer Register
Uartn_txbufr [8]: the eighth or even parity bits for data transmission, wake-up bits, or undefined bits are determined by the corresponding operation mode.
1. In 001 mode, this bit is written to 0.
2. If the 8 + verification 111 mode is used, the write operation of this bit by UART is invalid.
Uartn_txbufr [7]: The seventh or even parity bit of the transmitted data
1. If it is in 7 + verification 011 mode, the write software operation is not valid when the bit is processed by UART.
Uartn_txbufr [6:0]: Data bit

Uartn_rxbuffer: UART receiving register
RX [9]: token error flag 1 indicates that this token has a problem
RX [8]: receives 8 data bits, or parity bits or wake up bits.
RX [7]: receives data bit 7 or parity bit
RX []: Data bit

Uartn_cr: UART control register
Cr [15-11] is reserved as 0
Cr [10] disable oenble queue Mode 0 Closed indicates that txfifo considers that 16-bit data is contained in the full stack.
1 is enabled, indicating that txfifo considers the current is full stack and directly sets txfull bit.
Cr [9] 0 if scenble smart card is disabled or disabled
Cr [8] rxenble receiving function disabled enable rxd script initialization triggered by descent
Cr [7] Run = 0 baud rate useless = 1 is useful
Cr [6] loopback = 0 standard receiving and sending modes = 1 is a special mode. This bit is changed only when the UART is invalid.
Cr [5] parityodd select parity = 0 for parity = 1 for parity
Cr [43] stopbits 00 0.5 Stop bits 01 is 1 Stop bits 10 is 1.5 11 is 2
Cr [2: 0] mode 5 Modes

Uartn_ier UART interrupt permitted register
15-9 Reserved Bit is 0
8 rxhalffullie
7 timeoutidleie
6 timenotoutidleie
5 .. 1

Uart_sr UART Status Register
9. The txfull sending register contains 16 digits.
8 rxhalffull receives more than 8 digits
7 timeoutidle rxfifo is null and timeout
6 timenotoutidle rxfifo is not empty and timeout
5. The overrunerror data is being received and the receiving buffer is full.
4 framerror: when the receiving queue contains a flag of a receive Error
3 parityerror when the receiving queue contains a Validation Error
2 txhalfempty: half of the transmission queue is empty.
1 txempty transmission queue is empty

Uart_gtr UART protection occurrence time
The time value of 7-0 eight bits is defined by the user.ProgramDetection clock delay with null Transfer

Uart_tor UART timeout Mechanism
7-0 timeout loading counter

Uart_txrstr transfer register clearing register
Uart_rxrstr receive register clearing register
After writing only, the corresponding receiving or transfer register rxfifo or txfifo will be cleared.