[UART simple driver Introduction] the code is clearly annotated

Define general serial port structure
Typedef volatile struct
{
V2010br; // baudrate register, 16bit valid, mount the clock
V2010empty1; // retain 16-bit arm. 32-bit registers only use 16 bits.
V2010txbufr; // Transfer Register
V2010empty2;
V2010rxbufr; // receiving register
V2010empty3;
V2010cr; // control register
V2010empty4;
V2010ier; // interrupt register
V2010empty5;
V2010sr; // Status Register
V2010empty6;
V2010gtr; // time protection register
V2010empty7;
V2010tor; // timeout register
V2010empty8;
V2010txrstr; // reset the register of the transmission queue
V2010empty9;
V2010rxrstr; // reset register of the receiving queue
} Uart_typedef;

Serial Port usage Structure
Typedef Enum
{
Uart_rxfifo, // serial receiving queue
Uart_txfifo // serial sending queue
} Uartpolico_typedef; // queue Structure

Typedef Enum
{
Uart_even_parity = 0x0000, // odd check
Uart_odd_parity = 0x0020, // parity check
Uart_no_parity // no verification
} Uartparity_typedef; // check Structure

Typedef Enum
{
Uart_0_5_stopbits = 0x00, // The second-digit 05 Mode
Uart_1_stopbits = 0x08, // The second bit 1 Method
Uart_rj5_stopbits = 0x10, // The 15-digit mode.
Uart_2_stopbits = 0x18 // second bit 2 mode
} Uartstopbits_typedef; // struct

Typedef Enum
{
Uartm_8d = 0x01, // Data Transmission Mode 8 Data
Uartm_7d_p = 0x03, // data transmission mode 7 data
Uartm_9d = 0x04, // data transmission mode 9 Data
Uartm_8d_w = 0x05, // Data Transmission Mode 8 Data + wakeup Mode
Uartm_8d_p = 0x07 // Data Transmission Mode 8 Data + Verification Mode
} Uartmode_typedef; // data transmission mode structure

// ---- Use some definitions
// Sr flags definition, which is a bit corresponding to uartn_sr & Operation
# Define uart_txfull 0x0200 // 9bit
# Define uart_rxhalffull 0x0100 // 8bit
# Define uart_timeoutidle 0x0080 // 7bit
# Define uart_timeoutnotempty 0x0040 // 6bit
# Define uart_overrunerror 0x0020 // 5bit
# Define uart_frameerror 0x0010 // 4bit
# Define uart_parityerror 0x0008 // 3bit
# Define uart_txhalfempty 0x0004 // 2bit
# Define uart_txempty 0x0002 // 1bit
# Define uart_rxbuffull 0x0001 // 0bit

// Cr regiter bit Definition
# Define uart_1_oenablebit 10 //
# Define uart_rxenablebit 8
# Define uart_runbit 7
# Define uart_loopbackbit 6
# Define uart_parityoddbit 5
# Define uart_stopbits 3

// Stop bits Definition
# Define uart_05stopbits 0x00
# Define uart_1stopbit (0x01 <3)
# Define uart_15stopbits (0x02 <3)
# Define uart_2stopbits (0x03 <3)

// Modes Definition
# Define uart_8bitsdata 0x01 // mode data cr [2: 0] 001
# Define uart_7bitsdata 0x03 // mode data cr [2: 0] 011
# Define uart_9bitsdata 0x04 // mode data cr [2: 0] 100
# Define uart_8bitsdatawakeup 0x05 // mode data cr [2: 0] 101
# Define uart_8bitsdataparity 0x07 // mode data cr [2: 0] 111

// --- Implement functions
// Configure the UART Working Mode
Inline void uart_modeconfig (uart_typedef * uartx, uartmode_typedef uart_mode)
{
// Input the uartx structure and write it back to Cr Using the CR register [] & uart_mode in the Structure
Uartx-> Cr = (uartx-> Cr & 0xfff8) | (002) uart_mode;
}

// Configure the stop bit Detection Mode of UART
Inline void uart_stopbitsconfig (uart_typedef * uartx, uartstopbits_typedef stopbits)
{
// Cr [4: 3] & stop status write-back register
Uartx-> Cr = (uartx-> Cr & 0xffe7) | (002) stopbits;
}

// Set the UART Protection time
Inline void uart_guardtimeconfig (uart_typedef * uartx, 2010guardtime)
{
Uartx-> gtr = guardtime;
}

// Return the Status Register of the current UART
Inline 2010uart_flagstatus (uart_typedef * uartx)
{
Return uartx-> SR;
}

// Initialize UART operation
Void uart_init (uart_typedef * uartx)
{
Uartx-> ier = 0x00; // initialize the serial port interrupt register.
Uartx-> Cr = 0x00; // initialize the control register
(Void) uartx-> rxbufr;
Uartx-> rxrstr = 0 xFFFF; // clear the rxfifo shift register content
Uartx-> txrstr = 0 xFFFF; // clear the txfifo shift register content
}

// Configure the baud rate register
Void uart_baudrateconfig (uart_typedef * uartx, u32 baudrate)
{
Uartx-> Br = (002) (rccu_frequencyvalue (rccu_fclk)/(16 * baudrate ));
}

// Transmit one byte of data
Void uart_bytesend (uart_typedef * uartx, u8 * Data)
{
// If the fifo value in Cr is allowed, check whether the txfifo value is full 16 bits. If the FIFO value is full 16 bits, load and send data.
If (uartx-> Cr & (0x0001 <uart_1_oenablebit) // If FIFO Enabled
While (uartx-> Sr & uart_txfull); // while the uart_txfifo contain 16 characters.
// If the FIFO mode is not allowed to be disabled, the system can only detect that the txfifo mode is null and load and send data.
Else // If FIFO disabled
While (! (Uartx-> Sr & uart_txempty); // while the transmit shift register not empty
Uartx-> txbufr = * data;
}

// Receives one byte
Uart_bytereceive (uart_typedef * uartx, u8 * data, u8 timeout)
{
Wstatus;
// Input timeout size
Uartx-> tor = timeout; // reload the timeout counter
// Check whether the UART timeout is not time-out. It indicates that the data is being received, and rxfifo records the data into the receiving register.
While (! (Wstatus = uartx-> SR) & (uart_timeoutidle | uart_rxhalffull | uart_rxbuffull )));
* Data = (u8) uartx-> rxbufr; // then read the Receive Buffer register
Return wstatus;
}