VCS simulation generates FSDB files

vcs simulation generates FSDB files (Verilog) First, the environment

• Linux platforms
• VCS 64bit
• Verdi3

Second, start the simulation

1. Joint Simulation Environment Configuration

A. Add the following statement to the Testbench:

1 Initial begin 2     $fsdbDumpfile ("tb.fsdb"); 3     $fsdbDumpvars; 4 End

B. note the path to the Verdi interface library (as reflected in the script)

2. Simulation Script

1#!/bin/csh-F2 3Setenv novas_home/user/eda_tools/synopsys/verdi3-i-201403-SP14Setenv Novas_pli ${novas_home}/share/pli/vcs/LINUX645 setenv ld_library_path $NOVAS _pli6 7Setenv Novas"${novas_home}/share/pli/vcs/linux64"8 9Setenv Novas_args"- P $NOVAS/novas.tab $NOVAS/pli.a"Ten  OneVCs +v2k-sverilog +vcs+lic+wait-full64-debug_pp A+warn=nocdnyi,noipdw,noillgo,notmr,nophne,noiriid-W --mupdate +notimingcheck +nospecify - ${novas_args} the-F file.f -  -./SIMV

Generate Tb.fsdb file under current directory

3. Use Verdi to view waveforms

Verdi-f FILE.F-SSF Tb.fsdb &

VCS simulation generates FSDB files