Verilog HDL Study notes (basic concept)

1. as a hardware description language,Verilog can directly describe the hardware structure, but also by describing the system behavior to achieve modeling, its main features and functions are:

* describes basic logic gates and basic switch models.

* allow user-defined primitives.

* You can specify the port-to-port delay in the design, the path delay, and the timing check in the design.

* Models can be modeled in a variety of ways, including (1) Sequential Behavior Description Modeling-Using procedural structural modeling, (2) Data flow behavior-Modeling using continuous assignment statements, and (3) structured mode- Use the door and module instance statements to describe the modeling.

* There are two kinds of data types in Verilog , the wire mesh data type and the register data type. The wire mesh data type represents the wiring between components, while the register type represents an abstract data storage element.

* can describe hierarchical design, you can use the module instance structure to describe any hierarchy.

* not only can design description on RTL , but also can be described in architecture level and algorithm level behavior.

    * you can model the concurrency behavior and the timing behavior.

2. module

module is the most basic component of the Verilog HDL , the actual meaning of the modules is to represent the logical entities on the hardware circuit (a set of circuits that implement a particular logic function), which can range from a door to a large system. Modules are described in the form of behavioral modeling and structural modeling, which runs in parallel between modules. Module layering, each module connected to complete the system requires a top-level module.

Each system, no matter how complex, can always be divided into several small functional modules, the following steps:

(1) Divide the system into layer modules.

(2) plan the interface of each module.

(3) programming the module and connecting the modules to complete the system design.

Verilog HDL Enables the connection of sub-modules to high-level modules through module invocation (instantiation of modules).

The module instantiation is done by means of the structure modeling, the call of the sub-module inVerilog HDL is exactly "embed", this kind of reference will handle the module circuit completely in the high-level module.

3. Verilog HDL Drive is case-sensitive.

4. use parameter to declare parameters.

5. Common pre-processing directives:

' Define ' undef ' ifdef ' Else ' endef ' include ' timescale

6. Wire Mesh Data type: Indicates the physical connection between the components, it can not store data, the network is driven, can be used continuous assignment statement or the output of the component to the wire network to provide a drive to the wire network, to provide the driver of the network and the component is the driving source. Verilog HDL has one type of wire mesh.

7. Register represents an abstract data storage unit, you can change the value stored in the register by the assignment statement, the Register can only be assigned in the Always statement and initial , there are 5 types of register type values.

8. Data Flow Modeling is a simple behavior modeling, it has only one form, with the keyword "assign" Guided by a continuous assignment statement, its assignment target can only be a network, and this assignment behavior without any additional judgment conditions, Commonly used to describe combinatorial logic.

9. Modeling sequential behavior.

Structure Modeling method

Gate-level modeling and switch-level modeling are structural modeling methods in Verilog Hdlk , because their modeling is a specific description of the circuit structure. That is, the necessary basic circuit unit (logic gate,mos, switch) out, and then connect these basic units connected together, this description is simple and strict, must be on the bottom fin gate circuit and MOS tube Function and connection method familiar.

the gate circuit and MOS switch used for structural modeling are called "primitives", and theVerilog HDL has a built-in primitive model, which is called instantiation, and the invocation statement is also called an instance statement. Each time a primitive call produces an instance of the primitive, it should give the instance a name, that is, the instance name.

The structure description method also has an important use--call Submodule!!!

Verilog HDL Study notes (basic concept)