Verilog reading and outputting data from text to text

Verilog reading and outputting data from text to textReprinted 2016-10-18 10:14:22

Because it is often used, but every time to patchwork to remember how to write code. So it is to tidy up, after the use of the time to directly read this article.

1. Read the text data

Reading text data is written to the mem first, and then a single fetch is taken by the address of the control men. The sample code is as follows:

reg [11:0] data_src_mem [0:1023];//define a mem with a bit width of 12bit and a depth of 1024

reg [9:0] mem_addr;//define the address of the MEM

Wire [11:0] data;

Initial

Begin

$ READMEMH ("Path/data.txt", data_src_mem);//The Data.txt data under path path is 16 The binary form is written to the Data_src_mem.

End

Always @ (Posedge CLK or Negedge rst_n)

Begin

if (!rst_n)

Mem_addr <= ' D0;

Else

Mem_addr <= mem_addr + ten ' D1;

End

Assign data = Data_src_mem[mem_addr];

$ readmemh is written in 16 binary form and can also be written in binary form with $ readmemb. But how to write in decimal form I haven't found it yet.

2. Output data to Text

Integer out_file;//definition file handle

Initial

Begin

Out_file = $fopen ("Path/out_put_file.txt", "w"); Get file Handle

End

Always @ (condition)

...

$fwrite (Out_file, "%d", $signed (Reg_data));

......

Always wanted to output the decimal, did not find, later found to read the text data $signed this system function. It seems to be familiar with a lot of system functions, and then add these useful system functions to the article.