VHDL Design-Time parameter definition Method Example

--SPTB

LIBRARY IEEE;
Use Ieee.std_logic_1164.ALL;
Use IEEE. Std_logic_arith. All;
Use IEEE. std_logic_unsigned. All;
Use Std.textio.all;
Use Ieee.std_logic_textio.all;

--Uncomment the following library declaration if using
--arithmetic functions with signed or Unsigned values
--use IEEE.NUMERIC_STD. All;

ENTITY ROMTB is
--Component Declaration for the Unit under Test (UUT)
--generic (Init_0:bit_vector (downto 0): = X "0000");
PORT (
Do:out std_logic;
I0:in std_logic;
I1:in std_logic;
I2:in std_logic;
I3:in Std_logic
);
END ROMTB;

ARCHITECTURE Behavior of ROMTB is
COMPONENT ROM16
GENERIC (Init_0:bit_vector (downto 0): = X "0000");
PORT (
Do:out std_logic;
I0:in std_logic;
I1:in std_logic;
I2:in std_logic;
I3:in Std_logic
);
END COMPONENT;

BEGIN

UUT:ROM16 GENERIC MAP (init_0 = X "0000")
PORT MAP (
do = do,
I0 = I0,
I1 = I1,
I2 = I2,
I3 = I3

);

END;

VHDL Design-Time parameter definition Method Example