Video Signal Detection by Using OpenGL (external low frequency clock)

The younger brother is not familiar with the learning of OpenGL. This article is just a Summary of the entry level. Don't laugh at it. At the same time, this article is only a summary of my own small experience. The design ideas and procedures are for reference only.

In the past few days, I encountered a headache. A design requires that CPLD be used to detect the presence or absence of video signals, and the output level should be passed to the MCU for processing. The most important thing to consider is that the CPLD does not provide external clock signals at work, maybe to save costs. At the beginning, I thought there should be no problem. The VGA video signal has a line-field pulse signal, and this is not enough to trigger it. However, in practice, we find that this is not feasible. In case there is no pulse after the output is high, what should we do? Isn't it always high. I have been thinking about it for a long time, and I have asked a few friends, but I have not been able to solve it. Maybe the time is too short. You have not considered it carefully. Now, I think this is indeed the most basic problem. During this period, I thought that if an external clock is added, a high-frequency crystal oscillator, such as 50 m, can also be implemented through continuous sampling detection, but the hardware is not allowed now, think about other methods. With a friend's reminder (he has learned more than me, but the layers are different), he can give an external reset signal, because what I thought was to reset it with a field signal, and then I found this was a low-level error, you cannot operate on the same register variable in two triggering processes (this may be too much influenced by MCU programming thinking ). As a result, the program was re-designed with a clear mind. This time, the MCU was used to provide the reset signal for the CPLD, And the CPLD was used to reset the descent edge, and determine whether there is a video signal on the rising edge. Haha, the compilation is successful, and the download to the Board is completely OK !!! I would like to celebrate this little bit. I am also alert to myself. I have to think more about things. It is difficult to solve such a simple problem.

Module vga_detect (CLK, vin0, vin1, vin2, vin3, hin0, hin1, hin2, hin3, Vout, Hout, Sel, en, detect_out );



Input CLK;

Input en;

Input vin0;

Input vin1;

Input vin2;

Input vin3;

Input hin0;

Input hin1;

Input hin2;

Input hin3;

Input [2: 0] sel;



Output Vout;

Output Hout;

Output detect_out;



Reg Vout;

Reg Hout;

Reg [3: 0] detect_out;



Reg hin0_reg;

Reg hinw.reg;

Reg hin2_reg;

Reg hin3_reg;



Reg detect_flag0;

Reg detect_flag1;

Reg detect_flag2;

Reg detect_flag3;



Always @ (hin0 or hin1 or hin2 or hin3)

Begin

If (en = 0)
Begin
Case (SEL)
3 'b000: Begin
Vout <= vin0;
Hout <= hin0;
End
3 'b001: Begin
Vout <= vin1;
Hout <= hin1;
End
3 'b010: Begin
Vout <= vin2;
Hout <= hin2;
End
3 'b011: Begin
Vout <= vin3;
Hout <= hin3;
End
Default: Begin
Vout <= 0;
Hout <= 0;
End


Endcase
End
Else
Begin
Vout <= 0;
Hout <= 0;
End


End


//////////////////////////////////////// ////////////////////////

// Signal Detection

//////////////////////////////////////// /////////////////////


Always @ (posedge hin0 or negedge CLK)

Begin

If (hin0)
Begin
Detect_flag0 <= 1;
End
Else
Begin
Detect_flag0 <= 0;

End
 

End



Always @ (posedge hin1 or negedge CLK)

Begin

If (hin1)
Begin
Detect_flag1 <= 1;
End
Else
Begin
Detect_flag1 <= 0;

End
 

End



Always @ (posedge hin2 or negedge CLK)

Begin

If (hin2)
Begin
Detect_flag2 <= 1;
End
Else
Begin
Detect_flag2 <= 0;

End
 

End



Always @ (posedge hin3 or negedge CLK)

Begin

If (hin3)
Begin
Detect_flag3 <= 1;
End
Else
Begin
Detect_flag3 <= 0;

End
 

End



Always @ (posedge CLK)

Begin


If (detect_flag0 = 1)
Begin
Detect_out [0] <= 1;
End
Else
Begin
Detect_out [0] <= 0;
End
//////////////////////////
If (detect_flag1)
Begin
Detect_out [1] <= 1;
End
Else
Begin
Detect_out [1] <= 0;
End
////////////////////////////
If (detect_flag2)
Begin
Detect_out [2] <= 1;
End
Else
Begin
Detect_out [2] <= 0;
End
//////////////////////////////
If (detect_flag3)
Begin
Detect_out [3] <= 1;
End
Else
Begin
Detect_out [3] <= 0;
End


End

Endmodule