Vivado Timing Analysis Method--report_design_analysis (I.)

Report_design_analysis can be used to analyze the root causes of timing problems, and then find the appropriate timing optimization scheme to achieve the purpose of timing convergence.

I. Analyzing the timing violation path

The Vivado tool prioritizes timing optimization for the worst path, and ultimately does not necessarily become a critical path. Therefore, when analyzing the timing violation path, it is not just about the critical path. The following TCL command can report the worst 50 setup timing path.

Report_design_analysis-max_paths 50-setup

The timing report looks like this:

The logical delay (logic delay) and the line delay (Net delay) are the differences between the logic delay and line delay, and the direction of path analysis is slightly different.

1. Longer logic delay

A) Too many logic levels (logic levels): You can modify the code to increase the number of registers to reduce the logical progression

Report_design_analysis-logic_level_distribution-logic_level_dist_paths 5000-name design_analysis_prePlace// The distribution of logical series in analytical design

The above command can be used to analyze the distribution of logical series in the design, and then determine whether there is a logical series that does not meet the timing requirements. As the report shows, the design has a maximum logic delay of 5, and the recommended maximum logical progression differs depending on the clock frequency and device.

If you need to further determine the path with the longest logical progression, you can use the following command:

b) Existence of constraints such as Dont_touch or mark_debug that hinder the logical optimization of tools

c) a unit with long logic delay on the path, such as DSP and Bram

2, line delay longer

A) fan out larger: Add max_fanout option or modify code to manually copy high fan out signal

Report_high_fanout_nets-fanout_greater_than 50-max_nets 100

Executing the TCL command above can report a fan out of 100 longest paths greater than 50.

The command-generated report, as above, can analyze the fanout and drive types, recommending the maximum fanout associated with the device and design frequency.

For larger fanout, it is best to change to the storage output, as shown below the LUT output is not recommended.

b) The physical location is far away (for example, the pblock of different species)

c) Whether the SSI device has a cross-die signal

D) Congestion leads to abnormal line.

Can be seen through the device view, if the path is distorted, obviously not the optimal path, you can consider the congestion caused by the need to further analyze the region of the congestion program

Ii. Summary of Experiences

1, time series analysis should be carried through the whole process of comprehensive realization, after synthesizing can use report_design_analysis command to analyze the fan-out, logic series, and increase the iteration speed;

2, priority to the implementation of the default strategy, you can avoid excessive tool optimization design, to better expose the root cause of timing problems;

3, different devices, different design frequency, the recommended maximum logical series and fan out of different, such as UltraScale device, design frequency is greater than 400MHz, the longest logical series as far as possible to control under 3;

4, cross-SLR signal proposed source and the destination module of each storage level

Note: The reference document is "Ug906-vivado-design-analysis".

Vivado Timing Analysis Method--report_design_analysis (I.)