Vmx NON-ROOT operation & VM Entries & vmx support for address translation

Document directory

• 26.5.1 vectored-event Injection

Chapter 25 vmx NON-ROOT operation25.3 changes to instruction behavior in vmx NON-ROOT operation

• Mov from cr3. if the "enable EPT" VM-execution control is 1 and an execution of mov from 32a does not
Cause a VM exit (see section 25.1.3), the value loaded from 32a is a guest-physical address; see section
28.2.1.

• Mov to cr3. if the "enable EPT" VM-execution control is 1 and an execution of mov to H6 does not cause
VM exit (see section 25.1.3), the value loaded into 32a is treated as a guest-physical address; see section
28.2.1.

Chapter 26 VM entries26.5 event Injection

If the valid bit in the VM-entry interruption-information field (see section 24.8.3) is 1, Vm entry causes an event
Be delivered (or made pending) After all components of guest State have been loaded (including MSRs) and after
The VM-execution control fields have been established.
• If the interruption type in the field is 0 (External Interrupt), 2 (non-Maskable Interrupt); 3 (hardware
Exception), 4 (software interrupt), 5 (privileged software exception), or 6 (software exception), the event is
Delivered as described in section 26.5.1.
• If the interruption type in the field is 7 (other event) and the vector field is 0, an mtf vm exit is pending after
VM entry. See section 26.5.2.

26.5.1 vectored-event Injection

VM entry delivers an injected vectored event within the guest context established by VM entry. This means that
Delivery occurs after all components of guest State have been loaded (including MSRs) and after the VM-execution
Control fields have been established. The event is delivered using the vector in that field to select a descriptor in
The IDT. Since event Injection occurs after loading idtr from the guest-state area, this is the guest IDT.
Section 26.5.1.1 provides details of vectored-event injection. In general, the event is delivered exactly as if it had
Been generated normally.

Chapter 28 vmx support for address translation

The architecture for vmx operation between des two features that support address translation: Virtual-processor iden-
Tifiers (vpids) and the extended page-Table Mechanic (EPT). vpids are a mechanic for managing translations
Of linear addresses. EPT defines a layer of address translation that augments the translation of linear addresses.

28.1 virtual processor Identifiers (vpids)

Vmcs-> VM-EXECUTION control fields-> vpid

The current vpid is 0000 h in the following situations:
-Outside vmx operation.
-In vmx root operation.
-In vmx non-root operation when the "enable vpid" VM-execution control is 0.

28.2 The Extended page table Mechanic (EPT)

Some GLA are directly translated as HPA rather than GPa (GPA is translated as HPA again)
In this process, GLA first searches for the guset page table and then immediately finds the EPT paging ures to directly generate HPA instead of the GPA.

If cr0.pg = 1, the translation of a linear address to a physical address requires multiple translations of guest-phys-
Ical addresses using EPT. Assume, for example, that cr4.pae = cr4.pse = 0. The translation of a 32-bit linear
Address then operates as follows:
• Bits 31: 22 of the linear address select an entry in the guest page directory located at the guest-physical
Address in cr3. the guest-physical address of the guest page-directory entry (PVDF) is translated through EPT
To determine the guest P' s physical address.
• Bits 21:12 of the linear address select an entry in the guest page table located at the guest-physical address in
The guest PVDF. the guest-physical address of the guest page-table entry (PTE) is translated through EPT
Determine the guest PTE's physical address.
• Bits 11: 0 of the linear address is the offset in the page frame located at the guest-physical address in the guest
Pte. the guest-physical address determined by this offset is translated through EPT to determine the physical
Address to which the original linear address translates.