What is TTL level and CMOS level?

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What is TTL level?

TTL-level signals are used most often because they are represented in binary format. + 5 V is equivalent to logic "1" and 0 V is equivalent to logic "0 ", this is called a TTL (transistor-Transistor Logic level) Signal System, which is a standard technology for communication between various components of a device controlled by a computer processor.
TTL-level signals are ideal for data transmission within devices controlled by a computer processor. First, data transmission within devices controlled by a computer processor has low power supply requirements and low thermal loss, in addition, TTL-level signals are directly connected to integrated circuits without expensive line drivers and receiver circuits. Furthermore, data transmission within devices controlled by computer processors is carried out at high speeds, the TTL interface can meet this requirement. In most cases, TTL Communication adopts the parallel data transmission mode, and parallel data transmission is not suitable for a distance of more than 10 feet. This is because of both reliability and cost. Due to the biased and asymmetric problems in parallel interfaces, these problems have an impact on reliability. In addition, the cost of parallel data transmission, cables and connectors is higher than that of serial communication.

The level of the TTL circuit is called the TTL level, and the level of the CMOS circuit is called the CMOS level.
The full name of the TTL integrated circuit is the transistor-transistor logical Integrated Circuit (transistor-Transistor Logic), mainly including 54/74 series of standard TTL, High-Speed TTL (H-TTL), low-power TTL (L-TTL) five series: S-TTL and LS-TTL. The standard TTL input has a minimum high level of 2 V, an output high level of 2.4 V, a typical value of 3.4 V, an input low level of 0.8 V, an output low level of 0.4 V, and a typical value of 0.2 V. S-TTL input high level minimum 2 V, output high level minimum class I 2.5 V, Class II, Class III 2.7 V, typical value 3.4 V, input low level maximum 0.8 V, the maximum output level is 0.5 V. LS-TTL input high level minimum 2 V, output high level minimum class I 2.5 V, Class II, Class III 2.7 V, typical value 3.4 V, input low level maximum class I 0.7 V, class II and Class III 0.8 V. The maximum output is class I 0.4 V, Class II and Class III 0.5 V, and the typical value is 0.25 V. The power supply of the TTL circuit can only be in the range of + 5 V ± 10%, and the number of Fan outlets is less than 10 TTL door circuits;
Coms integrated circuits are short for complementary symmetric metal oxide semiconductors (compiementary oxide ry Metal Oxide semicoductor) integrated circuits, many basic logic units of the circuit are connected by an enhanced PMOS transistor and an enhanced NMOS tube in the form of complementary symmetry, with low static power consumption. The power supply voltage of COMS circuit VDD range is relatively wide in + 5 -- + 15 V can work normally, voltage fluctuation allows ± 10, when the output voltage is higher than the VDD-0.5V logic 1, the output voltage is less than VSS + 0.5 V (VSS is digit) and the logic is 0. The fan-out number is 10-20 coms gate circuits.
  TTL-level signals are used most often because they are represented in binary format. + 5 V is equivalent to logic "1" and 0 V is equivalent to logic "0 ", this is called a TTL (transistor-Transistor Logic level) Signal System, which is a standard technology for communication between various components of a device controlled by a computer processor. TTL-level signals are ideal for data transmission within devices controlled by a computer processor. First, data transmission within devices controlled by a computer processor has low power supply requirements and low thermal loss, in addition, TTL-level signals are directly connected to integrated circuits without expensive line drivers and receiver circuits. Furthermore, data transmission within devices controlled by computer processors is carried out at high speeds, the TTL interface can meet this requirement. In most cases, TTL Communication adopts the parallel data transmission mode, and parallel data transmission is not suitable for a distance of more than 10 feet. This is because of both reliability and cost. Due to the biased and asymmetric problems in parallel interfaces, these problems have an impact on reliability. In addition, the cost of parallel data transmission, cables and connectors is higher than that of serial communication. CMOS level and TTL level:
The CMOS level voltage ranges from 3 ~ 15 V. For example, when the 4000 Series is powered by 5 V, the output above 4.6 Is a high level, and the output below 0.05v is a low level. The input above 3.5v is a high level, and the input below 1.5v is a low level. For TTL chips, the power supply range is from 0 ~ 5 V, usually 5 V, such as 74 Series 5 V power supply, output above 2.7v is high level, output below V is low level, input above 2 V is high level, lower than 0.8v. Therefore, there is a problem of level conversion between the CMOS circuit and the TTL circuit, so that the level domain values of the two can match

Differences between TTL level and CMOS level

(1)TTLHigh Level 3.6 ~ 5 V, low 0 V ~ 2.4 V
CMOSLevel VCC can reach 12 V
CMOSThe output high level is about 0.9vcc, while the output low level is about 0.1vcc.
CMOSThe input end that is not used by the circuit cannot be left blank, which may cause logical confusion.
TTLThe input end not used by the circuit is suspended as a high level
In addition,CMOSThe power supply voltage of the integrated circuit can be changed in a large range, so the power supply requirements are notTTLThe integrated circuit is so strict.
UseTTLLevel, they can be compatible
(2)TTLThe level is 5 V,CMOSThe level is generally 12 V.
BecauseTTLThe circuit power supply voltage is 5 V,CMOSThe circuit power supply voltage is generally 12 V.
5 V level cannot be triggeredCMOSCircuit, 12 V level will be damagedTTLAnd therefore cannot be compatible with each other.
(3)TTLLevel standard
Output L: <0.4 V; H:> 2.4 v.
Input L: <0.8 V; H:> 2.0 V
TTLThe device output low level must be less than 0.4 V, and the high level must be greater than 2.4 v. If the input value is lower than 2.0 V, it is regarded as 0. If the input value is higher than, it is regarded as 1.

CMOSLevel:
Output L: <0.1 * VCC; H:> 0.9 * VCC.
Input L: <0.3 * VCC; H:> 0.7 * VCC.

Generally, single-chip microcomputer, DSP, and FPGA can directly communicate with each other. under normal circumstances, the same voltage is acceptable, but it is best to check the values of devil, VIH, vol, and voh in the Technical Manual to see if they can be matched (Vol is smaller than devil, voh must be greater than VIH, which is in a connection ). Some are normal in general applications, but the parameters are not matching enough. In some cases, they may not be stable enough, or different batches of devices cannot run.

For example, the output of the 74LS device is connected to the 74hc device. In general, it works well, but the parameters do not match, and in some cases it cannot be run. 

74LS and 54 series areTTLCircuit, 74hc isCMOSCircuit. If their serial numbers are the same, the logic functions are the same, but the electrical and dynamic performances are slightly different. For example,TTLThe logical high level of is> 2.7 V,CMOSIs> 3.6 V. IfCMOSThe first level of the circuit isTTLIt hides the potential for reliability, and vice versa.

1, TTL level:

  The output level is greater than 2.4 V, and the output level is less than 0.4 V. At room temperature, the output high level is generally 3.5 V, and the output low level is 0.2 V. Minimum input height and low level: Input height> = 2.0 V, input low level <= 0.8 V, and noise tolerance is 0.4 V.

2, CMOS level:

  1 logic level voltage is close to the power supply voltage, 0 logic level is close to 0 V. It also has a wide noise margin.

3. Level conversion circuit:

  Because TTL and coms have different high and low levels (TTL 5 V <=> CMOS 3.3 V), the level conversion is required when the two resistors are used for level partial pressure, there is nothing advanced. Haha

4, OC door, that is, open collector door circuit, OD door, that is, drain pole open door circuit, must be the external pull resistance and power supply in order to switch level as high and low level. Otherwise, it is generally used as the switch for large voltage and large current load, so it is also called the drive door circuit.

5. Comparison of TTL and COMS circuits:

1) the TTL circuit is the current controller, while the COMs circuit is the voltage controller.

2) the TTL circuit is fast, and the transmission delay is short (5-10ns), but the power consumption is high. The speed of the COMs circuit is slow, and the transmission delay is long (25-50ns), but the power consumption is low. The power consumption of the COMs circuit is related to the pulse frequency of the input signal. The higher the frequency, the hotter the chip set.

3) coms circuit locking effect:

  Because the input current of the COMs circuit is too large, the internal current increases sharply. The current keeps increasing unless the power supply is cut off. This effect is the locking effect. When the lock effect occurs, the internal current of COMS can reach more than 40mA, And the chip is easily burned out.

Defense measures:

1) Add a clamp circuit at the input and output ends so that the input and output voltage cannot exceed the specified voltage.

2) The power input of the chip is coupled with a decoupling circuit to prevent high voltage at an instant on the VDD end.

3) adds a line resistance between the VDD and the external power supply, and does not let it in even if there is a large current.

             

4) when the system is powered separately by several power supplies, the switch should be enabled in the following order: when the power supply is enabled, the COMs circuit is enabled first, and then the power supply of the input signal and load is enabled; when the power supply is disabled, first turn off the power of the input signal and load, and then turn off the power of the COMs circuit.

6. Precautions for using the COMs Circuit

  1) when the COMs circuit is used, the voltage controller has a high total input resistance and is capable of capturing interference signals. Therefore, do not leave unused pins empty. connect them to the pull resistance or drop-down resistance to give them a constant level.

  2) When the input end is connected to a low internal signal source, a throttling resistor must be connected between the input end and the signal source so that the input current is limited to 1mA.

  3) when the signal transmission line is connected to the COMs circuit, the resistance is matched.

  4) when the input end is connected to a large capacitor, the resistance should be indirectly protected at the input end and the capacitor. The resistance value is r = V0/1mA. v0 is the voltage on the external capacitor.

  5) if the input current of COMS exceeds 1mA, coms may be burned out.  

7. Load Characteristics at the input end of the TTL door circuit (Handling of special cases with resistance at the input end ):

  1) when it is suspended, it is equivalent to when the input end is connected to a high level. It can be seen that the input end is connected to an infinite resistance.

  2) input a low level after a 10 k resistor is connected at the input end of the door circuit. The input end shows a high level rather than a low level. According to the load characteristics at the input end of the TTL door circuit, the low-level signal input by the TTL door circuit can be identified only when the series resistance connected to the input end is less than 910 euros, if the series resistance is large, the input end will always be high. Pay attention to this. The COMS door circuit does not need to consider this.

8. The TTL circuit has an open-collector OC gate, and the mos tube also has an open-drain OD gate corresponding to the Collector. Its output is called an open-drain output. The OC door has a leakage current output at the end, that is, the leakage current. Why is there a leakage current? That is because when the end of the three-host tube, its base current is about equal to 0, but it is not really 0. The current of the collector passing through the transistor is not really 0, but about 0. This is the leakage current. Open/leak output: the output of the OC gate is the open/leak output, and the output of the OD gate is also the open/leak output. It can absorb a large amount of current, but cannot output the current outward.

Therefore, in order to be able to input and output current, it must be used together with the power supply and the pull-up resistor. The OD gate is generally used as an output buffer/driver, a level converter, and can meet the needs of absorbing large load current.

9. What is the Tumen pillar? What is the difference between it and the open-leakage Road?

  In the TTL integrated circuit, the output with a pulling transistor is called the tengzhu output, but not the OC gate. Because TTL is a third-level off, the chart column is connected by two third-level tubes. So pushing and pulling is a totem.