Xilinx FPGA entry Serial 37:sram read-write Test timing interpretation

1 SRAM Read-Write timing interpretation

Memory is overwhelming, and is the size of the computer system (including embedded systems) is not a small part. It is no exaggeration to say that there must be a data transfer process where there is memory, whether it is embedded in the CPU or plug-in, in the code store or program running when it must be necessary. In this section, the experimental object SRAM (Static RAM) is an asynchronous transmission of volatile memory, its read and write transmission faster, control timing is not complex, so there is a very wide range of applications.

You find the datasheet of any SRAM chip, you will find that their timing operation is much the same, here to summarize some of their common things, but also some of the simple fast operation of SRAM with Verilog techniques. The structure of the internal SRAM as shown, to access the actual Momory region, the FPGA must send the address (A0-A14) and control signal (ce#\oe#\we#), SRAM internally with this corresponding address decoding (decoder) and control processing circuit Circuit). In this way, data on the bus (I/O0-I/O7) can be read or written accordingly.

The example of is62lv256-45u used in this experiment is described here. The PIN definition is as shown in the table.

Serial number	Pin	Direction	Describe
1	A0-a14	Input	Address bus
2	CEn	Input	Chip enable input, low effective.
3	OEn	Input	Output enable input, low effective.
4	WEn	Input	Write enable input, low effective.
5	I/o0-i/o7	Inout	Data input/Output bus.
6	Vcc	Input	Power.
7	GND	Input	Digital ground.

The hardware schematic diagram of this design is shown in the figure.

Figure 6.59 SRAM Interface

For the read operation timing of the SRAM, the waveform is shown in the figure.

For the SRAM write operation timing, the waveform is shown in the figure.

The specific operation is this, to write data, (here is relative to the use of FPGA operation SRAM, software read and write may have time-order issues to note), more efficient operation is to send data and address, ce# and we# pull down. Then the delay time again ce# and we# pull high, then the data written to the corresponding address, so simple. Read the data is more simple, as long as the need to read the address on the SRAM address bus, the ce# and oe# pull down, and then delay time to read the data.

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