Xilinx Vivado Usage Details (3): Using the IP Core

Ilinx Vivado Usage Details (3): Using the IP Core

Author:zhangxianhe

IP Nuclear ( IP Core )

There are many IP cores in Vivado that can be used directly, such as mathematical operations (multipliers, dividers, floating point arithmetic, etc.), signal processing (FFT, DFT, DDS, etc.). IP core similar programming in the function library (for example, C language in the printf () function), can be directly called, very convenient, greatly accelerated the development speed.

mode one: Use Verilog called IP Nuclear

Here is a simple example of the IP core usage of a multiplier, which is called using Verilog. Start with a new project and create a new DEMO.V top-level module. (Process reference Previous document)

Adding IP Cores

Click IP Catalog in the Flow navigator.

Select the multiplier under Math functions, which is the multiplier, and double-click.

The Parameter Settings dialog box for the IP core pops up. Click on the documentation in the upper left corner to open the user manual for this IP core. Here directly set the input signal A and B are 4-bit unsigned data, the other is the default value, click OK.

To pop up the window later, click Generate. The generated dialog box is directly click OK.

The global representation in the synthesis option only generates RTL code and then participates in the synthesis with the entire project, and the out of context per IP represents the immediate synthesis after the build.

Call the IP Core

Select IP Sources, expand and select Mult_gen_0-instantiation Template-mult_gen_0.veo to open the instantiation template file. , this code is a sample code that calls this IP core using Verilog.

Copy the sample code into the DEMO.V file and modify it as follows. The code declares unsigned 4-bit variables A and B, assigning the initial value 7, 8, used as a multiplier, and the unsigned 8-bit variable p, which holds the result of the calculation. CLK 20ns clock signal written for testbench; Mult_gen_0 mymult_gen_0 (...) The MULT_GEN_0 statement instantiates a Module object of type Mymult_gen_0 and passes CLK, a, B, p as parameters.

1 ModuleDemo (2 );3 RegCLK =0;4  always#TenCLK = ~CLK;5  Wire[3:0] A =7;6  Wire[3:0] B =8;7  Wire[7:0] p;8 mult_gen_0 mymult_gen_0 (9. CLK (CLK),//input Wire CLKTen. A (a),//input wire [3:0] A One. B (b),//input wire [3:0] B A. P (p)//output wire [7:0] P - ); - Endmodule

Behavioral Simulation Verification

The demo is the top-level module, and the waveform can be output by initiating the behavior simulation. Set A, B, and p to display as unsigned decimal (right-click to select radix-unsigned decimal). , you can see A=7, b=8, the first clock rising along after P = A * b = 56.

Mode two: Block Design calls the IP core

Here is a simple example, by invoking the multiplier IP core, to generate a new module that can calculate the square.

Create a block diagram design file

Select Create block design in the Flow Navigator, creating a block diagram file.

Enter a file name and click OK.

Adding IP Cores

By starting the Add IP Wizard, or you can right-click in the blank of the program diagram to select the Add Ip..,ip directory window will appear, displaying all possible IPs in this design.

The IP core can be added in to connect it to other devices with wire.

Double-click the IP core symbol to open the Parameter Settings dialog box. Click on the documentation in the upper left to view the IP core manual. Here will enter a, B are set to 4 is unsigned, the other is the default value, click OK to confirm.

Drawing circuit

Right-click the Diagram window in the blank space and select Create Port.

In the pop-up window, set port A to 4-bit input signal and click OK.

Connect A and A and B together.

In the same way, add a 8-bit output port p, which is connected to P.

Add a CLK clock input port and connect to CLK.

The final result.

Click Tools, select Click Validate Design, check the program block diagram for errors, and click OK directly.

Simulation test

In the source pane, select the system block Diagram "system.bd", right-click and select Generate Output products, default settings, direct point generate, after the run is finished, click OK.

In the source pane, select the system block Diagram "system.bd", right-click and select Create HDL Wrapper, select the second let Vivado manage Wrapper and Auto-update, The difference between selecting the first item and the second item is to select the first item that represents the generated wrapper to allow the user to edit, select the second item to allow Vivado to manage wrapper, and update automatically, and the user's modifications to wrapper will be overwritten with the re-created HDL wrapper. Select the first item if the generated wrapper needs to be modified, depending on the circumstances of your design. Click OK.

Open the generated system_1_wrapper.v file, and the code in the red box is used to invoke the block design module that was previously drawn.

In the SYSTEM_1_WRAPPER.V file, you add the Testbench code to perform a behavioral simulation. Modify the code as follows, give the input signal a to the initial value of 8,CLK connected to the testbench generated clock signal c.

1 ModuleSystem_wrapper2 (A,3 CLK,4 p);5   input[3:0]a=8;6   inputCLK;7   Output[7:0]p;8    Wire[3:0]a;9    WireCLK;Ten    Wire[7:0]p; One   Regc =0; A    always#TenC <= ~C; -   AssignCLK =C; - system System_i the (. A (a), - . CLK (CLK), - . P (p)); - Endmodule

Start the behavior simulation, the final output waveform is as follows. As you can see, after the first rising edge of CLK, there is P = A*a = 64, which implements the square operation.

Call the official other IP core, the method is consistent, what questions welcome the guidance of communication.

Xilinx Vivado Usage Details (3): Using the IP Core