Branch delay slot in MIPS

Branch delay slot in MIPS

I bought the Chinese version of the "see MIPS run Linux". The translated sentence is useless. The first chapter won't be able to read any more, and the more critical the location is.

Http://hi.baidu.com/comcat/blog/item/c6f4f909cf551bc53ac76359.html

1. Overview

Branch delay slot is simply a command behind the branch command. It is always executed no matter whether the branch occurs or not, in addition, commands in the branch delay slot are submitted before the branch commands (COMMIT ).

Read this code snippet (MIPs Linux kernel 2.6.17 ):

801ea9d4: 02202021 move A0, S1
801ea9d8: 27a50014 addiu A1, SP, 20
801ea9dc: 0c0ce551 Jal 80339544 <pcibios_resource_to_bus>
801ea9e0: 02403021Move A2, S2


801ea9e4: 8e240010 LW A0, 16 (S1)
...

According to MIPS Abi, when A0, A1, A2, and A3 are used for the first four parameters of a process call, move A2 and S2 sets 3rd parameters, but it is located after the function call command Jal 80339544 (branch command), the move A2, S2 location is a branch delay slot.

Branch delay slots are common in DSPs and long-history FPGAs, such as MIPS and iSCSI. This concept is not available on powerpc and arm. X86 is also unavailable.

2. Origin

The main purpose of introducing branch delay slots is to improve pipeline efficiency.

In the pipeline, when the branch command is executed, the target address of the next command is determined (followed by or directed to the target ?) Generally, it is up to 2nd
After the level, the fetch level of the pipeline cannot work before the target is determined, that is, the entire pipeline is "wasted" (blocking) A time slice, in order to use this time slice, after the redirection command is specified at the level of the Architecture
A time slice above is a branch delay slot (branch Delay
Slot ). The commands in the branch delay slot are always executed and have no relationship with the occurrence of the branch. In this way, a time slice is effectively used to eliminate a "bubble" of the pipeline ".

This technical method is mainly used in the early stage of the pipeline without branch prediction, and in the modern stage, it has long been possible to determine the jump target by using branch prediction at level 2nd of the pipeline, the branch delay slot loses its original value, but it is retained for the software compatibility MIPS and PowerPC.

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Q2: Why is the returned address of the previous instruction abnormal in the delay slot?
A2:
To put it simply, the branch jump command flow of the CPU is generally the branch jump command-> the target jump address command.
However, the MIPs branch jump command flow is: The Branch jump command-> the delay slot command-> the target jump address command, and the delay slot command is inserted in the intermediate operation.
If the instruction address of the delay slot returned when the PC is interrupted after the delay slot address is interrupted, the re-executed instruction flow is: delay slot instruction-> (delay slot instruction address + 4) address command, no jump!
This is not the original interrupted command flow. To restore the original command flow, you need to reload the jump command in front of the delay slot into the pipeline.
Therefore, the address returned after the delay slot is interrupted is the address of the previous jump command.

Q4: whether the asid is true or not, and how the virtual address is translated
A4:
1) when the G bit is 1, the asid field is invalid if the asid field is not checked. The shared memory implementation between processes depends on this G bit.
2) virtual address translation process:
Send the virtual address page number and the asid of the process to MMU.
MMU checks whether all TLB items have matched items. The matching process is as follows (assuming pagemark ):
Match entryhi first. If vpn2 is equal and asid is equal or G bit is 1, entryl0 (LSB bit is 0) or entryl1 (LSB bit is 1) is obtained based on the partition bit of the page table ), if it does not match, a TLB missing exception is thrown.
Then match entrylx. If the V bit is zero, a TLB invalid exception is thrown. If the D bit is zero and it is a write operation, a TLB modification exception is thrown. The OS should use this to implement write and copy.
Finally, the page offset of PFN and virtual address in entrylx is combined into the actual physical address.

Q5: How to put two consecutive pages of virtual addresses but non-sequential physical addresses in the same TLB
A5:
When a process applies for two consecutive virtual pages, the corresponding physical pages may be continuous or discontinuous. At the same time, create a new page table item in the memory.
When an address in the range of virtual addresses needs to be translated, this page table item is transferred from memory to TLB.
For Linux kenerl, because of the write-time copy policy, the corresponding physical page cannot be allocated when a virtual page is applied, as described in qa4.

Q6: What is the function of the c Field in TLB?
A6:
According to the description of see MIPS run 2nd, it should be used to solve the problem of multi-processor cache synchronization. The original Article is as follows:
A 3-bit field originally defined for Cache-coherent Multiprocessor
Systems to set the "cache algorithm"

Q7: Shadow register heap Function
A7:
Generally, the CPU needs to save the CPU context and the CPU register before the interrupt processing program starts.
MIPs provides a hardware register group stack, which allows you to set the CPU to use a new register group when it enters the interrupt, saving the general process of the CPU storing the register group in the software stack, shorten the interrupt processing time.

Q8: exl and ERL are different.
A8:
In my personal understanding, exl is mainly caused by logic, such as various TLB exceptions.
Erl is mainly caused by physical errors, such as cache check errors.