Makefile file authoring and use of Autotools

Source: Internet
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In Linux or UNIX environments, For small programs that contain only a few source code files (such as hello.c), you can manually type the GCC command to compile the source code files one by one; however, in large project development, it may involve dozens of to hundreds of source files, compiled by manual typing, it is very inconvenient, and once changed the source code, especially the header file occurred modification, manual compilation and maintenance of the workload is quite large, and error-prone. So in Linux or UNIX environments, people often use the GNU make tool to automate the maintenance and compilation of applications. In fact, the GNU make tool accomplishes automatic maintenance and compilation of the application through a file called Makefile. Makefile is a text file written in some script syntax, and GNU make is able to interpret the instructions in the makefile and perform the compile operation. The makefile file defines a series of rules that specify which files need to be compiled first, which files need to be compiled, which files need to be recompiled, and even more complex functional operations. The following steps are performed when GNU make works:

    1. Read into all the makefile.
    2. Read the other makefile that are included.
    3. Initializes a variable in the file.
    4. Derive the cryptic rules and analyze all the rules.
    5. Create a dependency chain for all the target files.
    6. Depending on the dependencies, decide which targets to regenerate.
    7. Executes the build command.

1-5 steps for the first stage, and 6-7 for the second stage. In the first stage, if the defined variable is used, make will expand it to the location in use. But make does not start all at once, making uses procrastination tactics, and if a variable appears in a dependency rule, the variable will be expanded within it only if the dependency is determined to be used. The following is a brief introduction to Makefile's related issues.

The basic structure of makefile

General structure of the makefile:

Target ... : Dependency ...
Command ...

Meaning of the parts in the structure:
1. Target: A target file, which can be an object file or an executable file. It can also be a label.
2. Dependency (dependent): Which files to generate the target file depends on
3. Command: The shell command to run when the project is created (note: The indentation of each line in the command section must be tab-and not multiple spaces).

Makefile is actually a dependency of a file, that is, target one or more of the destination files depend on the files in dependency, and their generation rules are defined in command commands. If more than one file in the dependent file (dependency) is newer than the target file, the command defined by the shell command is executed. This is the rule of makefile. This is the core content of makefile.

For example, if you have a C source file test.c that contains a custom header file Test.h, the target file TEST.O explicitly relies on two source files: test.c and test.h. If you only want to use the GCC command to generate the TEST.O target file, you can use the following makefile to define the TEST.O creation rule:

#This makefile just is a example. test.o: test.c test.h    gcc –c test.c

Note from the above example that the first line with a # is the comment line. The first non-comment line specifies TEST.O as the target, and depends on the test.c and test.h files. The subsequent lines specify how to establish a target from the file that the target depends on.

When the test.c or test.h file is modified after compilation, the Make tool can automatically recompile the TEST.O, and if the test.c and test.h are not modified between the previous and two compilations, and TEST.O exists, there is no need to recompile. This dependency is especially important in program compilation of multi-source files. With this dependency definition, the Make tool avoids a lot of unnecessary compilation work.

You can define multiple targets in a makefile file, use the make target command to specify the target to compile, and if you do not specify a target, use the first target. Typically, a clean target is defined in makefile, which can be used to clear intermediate files during compilation

# This makefile just is a example. test.o: test.c test.h    gcc -c  test.cclean:    rm -f *.o

When you run make clean, execute the rm–f *.o command to remove any intermediate files that are generated during compilation.

Basic content of Makefile

Makefile generally includes five elements: explicit rules, cryptic rules, variable definitions, file indications, and annotations.
1. Explicit rules: Explicit rules describe how to generate one or more target files. This is clearly indicated by the writer of the makefile, to generate the file, the file's dependent file, the generated command.
2. Variable definition. In makefile, you can define a series of variables, which are usually strings, and when Makefile is executed, the value of the variable is extended to the corresponding reference position.
3. Implied rule: Since GNU make has an automatic derivation function, the cryptic rule can write makefile in a rough manner, and then the content of the cryptic rule is completed by the auto-derivation function of GNU make.
4. Documentation instructions. It consists of three parts, one referencing another makefile in one makefile, just like the include in C, and the other is specifying a valid part of makefile based on certain circumstances, just like the precompiled # if in C language And there is a command that defines a multiline.
5. Comments. Makefile is only a line comment, like the Unix shell script, its comments are "#" characters, if you want to use the "#" character in your makefile, you can escape with a backslash, such as: "\#".

Variables in the Makefile
    1. The variable defined in makefile, like a macro in C + + language, represents a text string that is automatically expanded where it is used when makefile is executed. Variables in makefile can be used in "target", "dependent target", "command" or other parts of makefile.
    2. The names of variables in makefile can contain characters, numbers, underscores (which can be the beginning of a number), but should not contain ":", "#", "=", or null characters (spaces, carriage returns, etc.).
    3. The variables in makefile are case-sensitive, and "foo", "foo", and "foo" are three different variable names. The traditional makefile variable names are all-uppercase naming methods.
    4. Variables need to be given an initial value when declared, and in use, a "$" symbol must precede the variable name
# makefile test for hello program#written by EmdoorCC=gccCFLAGS=OBJS=hello.oall: hellohello: $(OBJS)    $(CC) $(CFLAGS) $(OBJS) –o hellohello.o: hello.c    $(CC) $(CFLAGS) –c hello.c –o $(OBJS)clean:    rm –rf hello *.o

The above custom variable OBJS represents hello.o, and when Makefile is executed, the variable is expanded exactly where it was used, just like a macro in C + +. The above Makfile variable is expanded in the following form:

# makefile test for hello program#written by EmdoorCC=gccCFLAGS=OBJS=hello.oall: hellohello: hello.o    gcc  hello.o –o hellohello.o: hello.c    gcc –c hello.c –o  hello.oclean:    rm –rf hello *.o
Main pre-defined variables for GNU make
GNU make 有许多预定义的变量,这些变量具有特殊的含义,可在规则中使用。以下给出了一些主要的预定义变量,除这些变量外,GNU make 还将所有的环境变量作为自己的预定义变量。[email protected] ——表示规则中的目标文件集。在模式规则中,如果有多个目标,那么,"[email protected]"就是匹配于目标中模式定义的集合。$% ——仅当目标是函数库文件中,表示规则中的目标成员名。例如,如果一个目标是"foo.a(bar.o)",那么,"$%"就是"bar.o","[email protected]"就是"foo.a"。如果目标不是函数库文件(Unix下是[.a],Windows下是[.lib]),那么,其值为空。$< ——依赖目标中的第一个目标名字。如果依赖目标是以模式(即"%")定义的,那么"$<"将是符合模式的一系列的文件集。注意,其是一个一个取出来的。$? ——所有比目标新的依赖目标的集合。以空格分隔。$^ ——所有的依赖目标的集合。以空格分隔。如果在依赖目标中有多个重复的,那个这个变量会去除重复的依赖目标,只保留一份。$+ ——这个变量很像"$^",也是所有依赖目标的集合。只是它不去除重复的依赖目标。
Variables of the command
AR  函数库打包程序。默认命令是“ar”。 AS    汇编语言编译程序。默认命令是“as”。CC  C语言编译程序。默认命令是“cc”。CXX  C++语言编译程序。默认命令是“g++”。CO    从 RCS文件中扩展文件程序。默认命令是“co”。CPP C程序的预处理器(输出是标准输出设备)。默认命令是“$(CC) –E”。FC  Fortran 和 Ratfor 的编译器和预处理程序。默认命令是“f77”。GET 从SCCS文件中扩展文件的程序。默认命令是“get”。 LEX  Lex方法分析器程序(针对于C或Ratfor)。默认命令是“lex”。PC    Pascal语言编译程序。默认命令是“pc”。YACC    Yacc文法分析器(针对于C程序)。默认命令是“yacc”。YACCR    Yacc文法分析器(针对于Ratfor程序)。默认命令是“yacc –r”。MAKEINFO    转换Texinfo源文件(.texi)到Info文件程序。默认命令是“makeinfo”。TEX    从TeX源文件创建TeX DVI文件的程序。默认命令是“tex”。TEXI2DVI    从Texinfo源文件创建军TeX DVI 文件的程序。默认命令是“texi2dvi”。WEAVE    转换Web到TeX的程序。默认命令是“weave”。CWEAVE     转换C Web 到 TeX的程序。默认命令是“cweave”。TANGLE    转换Web到Pascal语言的程序。默认命令是“tangle”。CTANGLE    转换C Web 到 C。默认命令是“ctangle”。RM  删除文件命令。默认命令是“rm –f”。
Command parameter variables
下面的这些变量都是相关上面的命令的参数。如果没有指明其默认值,那么其默认值都是空。ARFLAGS     函数库打包程序AR命令的参数。默认值是“rv”。ASFLAGS     汇编语言编译器参数。(当明显地调用“.s”或“.S”文件时)。 CFLAGS     C语言编译器参数。CXXFLAGS     C++语言编译器参数。COFLAGS     RCS命令参数。 CPPFLAGS     C预处理器参数。( C 和 Fortran 编译器也会用到)。FFLAGS    Fortran语言编译器参数。GFLAGS     SCCS “get”程序参数。LDFLAGS    链接器参数。(如:“ld”)LFLAGS     Lex文法分析器参数。PFLAGS Pascal语言编译器参数。RFLAGS     Ratfor 程序的Fortran 编译器参数。YFLAGS     
Implied rules
GNU make 包含有一些内置的或隐含的规则,这些规则定义了如何从不同的依赖文件建立特定类型的目标。 GNU make 支持两种类型的隐含规则:1.2. 模式规则(pattern rules)。这种规则更加通用,因为可以利用模式规则定义更加复杂的依赖性规则。模式规则看起来非常类似于正则规则,但在目标名称的前面多了一个 % 号,同时可用来定义目标和依赖文件之间的关系,例如下面的模式规则定义了如何将任意一个 X.c 文件转换为 X.o 文件: %.c:%.o $(CC) $(CCFLAGS) $(CPPFLAGS) -c -o [email protected] $<
Run make

In general, the simplest is to directly enter the make command at the command line, GNU make to find the default makefile rule is to find three files in the current directory-"Gnumakefile", "Makefile" and "makefile". In order to find the three files, once found, it began to read the file and executed, you can also give the Make command to specify a special name of the makefile. To achieve this function, the "-F" or "--file" parameter of make is required, for example the special name is Makefile1, then the command is: Make–f makefile1

Autotools principle

Makefile can help make complete its mission, but writing makefile is certainly not an easy task, especially for a larger project. So, is there an easy way to generate makefile and at the same time allow us to enjoy making the advantages? This experiment to talk about Autotools series tools is designed for this, it just user input simple target file, dependent files, file directory, etc. can easily generate makefile, this is undoubtedly the vast number of users hope. In addition, these tools can also complete the collection of system configuration information, so as to easily handle a variety of portability issues. It is based on this, now Linux software development is generally used autotools to make makefile.

First, what is the GNU Autotools
The GNU Autotools consists mainly of the following three tools:
autoconf– This tool is used to generate configure scripts. As mentioned earlier, this script is primarily used to analyze your system to find the right tools and libraries. For example: Is your system's C compiler "CC" or "gcc"?
automake– This tool is used to generate makefiles. It needs to use the information provided to autoconf. For example, if autoconf detects that your system uses "GCC", then makefile uses GCC as the C compiler. Conversely, if "CC" is found, then "CC" is used.
libtools– This tool to create a shared library. It is platform-independent.

Second, Autotools use process

Autotools is a series of tools, first make sure the system is loaded with the following tools (can be viewed with the which command).


The main use of Autotools is to use the script files of each tool to generate the final makefile. The overall process is this:
1) Use aclocal to generate a "aclocal.m4" file that mainly handles local macro definitions;
2) Overwrite the "Configure.scan" file and rename it to "" and use the autoconf file to generate the Configure file.

Use Autotools to automatically generate makefile files to create HELLO.C, hello.h files with a text editor
//hello.c//written by Emdoorint main(){    printf("Welcome Emdoor!\n");    return1;}//hello.h#include <stdio.h>
Use AutoScan to generate Configure.scan edit Configure.scan, modify related content, and rename it to

Use aclocal build ACLOCAL.M4 use autoconf build Configure use Autoheader build edit

This step is an important step in creating makefile, and the script configuration file Automake to use is, and the user needs to create the file himself. After that, the Automake tool transforms it into a

AUTOMAKE_OPTIONS=foreignbin_PROGRAMS=hellohello_SOURCES=hello.c hello.h
Generate using Automake


Generate Makefile using Configure


In this step, the is turned into the final makefile by running the automatic configuration settings file configure

Using make to generate a hello executable file


Install hello into the system directory using make install

Make install

Use make dist to generate a Hello compression package to extract the Hello compression package

Tar-xzf hello-1.0.tar.gz

Go to unzip directory and install hello software in this directory

Make install

Almost so many, in fact, are embedded in the experiment part of the content, write down only for memories.

Makefile file Authoring and Autotools use

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