Makefile Study Notes

The process of making processing makefile is also divided into two stages:

· First read all the rules from the front to the back to create a complete dependency diagram

· Then, starting with the target specified by the default target or command line, and choosing the appropriate rule execution based on the dependency graph, the rules in the execution makefile are not executed sequentially from the front to the back, and not all rules are executed again. All of its conditions are updated first, and the target must be updated as soon as one of the conditions is updated.

Write makefile are goal-centric, a goal depends on a number of conditions, and now a different angle, the following condition-centric (makefile purpose is to let make build a dependency graph, as long as all the dependencies are described clearly OK)

MAIN.O stack.o:stack.h

MAIN.O STACK.O Maze.o:main.h

MAIN.O maze.o:maze.h

Note: Specifying a target (such as clean) on the Make command line updates the target and updates the target of the first rule in makefile (the default target) if you do not specify a target.

Tip: The command is preceded by the @ and-character: if make executes a command preceded by the @ character, the command itself is not displayed and only the result is displayed; Make executes the command to terminate immediately if an error occurs, no further commands are executed, but if the command is preceded by a-number, even if the command fails, Follow-up commands. The RM command and the mkdir command are usually preceded by a plus-sign.

Makefile contains five main things: explicit rules, cryptic rules, variable definitions, file instructions, and annotations. ）

By default, the make command searches the current directory for files named "Gnumakefile", "Makefile", "Makefile", and finds explanations for this file. In these three file names, it is best to use the "Makefile" file name, the first character in uppercase has a sense of purpose. It is best not to use "Gnumakefile", which is the GNU make recognition. There are other make that are only sensitive to the "makefile" file name in full lowercase, but basically, most of them support both the "makefile" and "makefile" default filenames.

Of course, you can use a different file name to write makefile, such as: "Make.linux", "Make.solaris", "Make.aix", etc., if you want to specify a specific makefile, you can use make "-F" and "--file" parameters , such as: Make-f make.linux or make--file Make.aix.

One: Explicit rules.

Explicit rules describe how to generate one or more target files. This is clearly indicated by the writer of the makefile, to generate the file, the file's dependent file, the generated command.

The rule contains two parts, one is a dependency, and the other is the method that generates the target.

Target.o:target.c target.h

Gcc-c Target.c-o TARGET.O

File TARGET.O depends on target.c and target.h files, if the file date of target.c and target.h is newer than the TARGET.O file date, or TARGET.O does not exist, then the dependency occurs.

Second, the obscure rule (make of the implied rules database can be printed with the Make-p command).

All conditions that a target depends on are not necessarily written in one rule, but can also be disassembled (if a goal is to open multiple rules where only one rule has a list of commands, other rules should have no command list, otherwise make will report a warning and a command list with the last rule).

Target.o:target.h

Target.o:target.c

Gcc-c Target.c-o TARGET.O

Make has the function of automatic derivation, using the obscure rule can write makefile briefly.

The above is equivalent to:TARGET.O:target.h (Makefile will attempt to build an implicit command if no command is compiled)

The variables used in the implied rules are divided into two kinds: one is command-related, such as "CC", and the other is the close of the parameter phase, such as "CFLAGS".

Variables for the command: ar  function Library Packager. The default command is "AR".   as  assembly language compiler. The default command is "as". cc  C language Compiler program. The default command is "CC". cxx  C language Compiler program. The default command is "G". co  extends the file program from the RCS file. The default command is "CO". cpp  C program's preprocessor (output is standard output device). The default command is "$ (CC) –E". fc  Fortran and Ratfor compilers and pre-processing programs. The default command is "F77". get  The program that extends the file from the SCCs file. The default command is "get".   lex  LEX Method Parser Program (for C or ratfor). The default command is "Lex". pc  Pascal Language Compiler program. The default command is "PC". yacc  YACC Grammar Analyzer (for C programs). The default command is "YACC". yaccr  YACC Grammar Analyzer (for ratfor programs). The default command is "Yacc–r". makeinfo  Convert the Texinfo source file (. texi) to the info file program. The default command is "Makeinfo". tex  A program that creates a Tex DVI file from a Tex source file. The default command is "Tex". texi2dvi  the program to create the Army Tex DVI file from the Texinfo source file. The default command is "Texi2dvi". weave  Convert Web to Tex program. The default command is "weave". cweave  convert C Web to Tex program. The default command is "Cweave". tangle  convert Web to Pascal language program. The default command is "Tangle". ctangle  convert C Web to C. The default command is "Ctangle". rm  the Delete file command. The default command is "Rm–f".

Variables for command arguments: The variables below are all parameters related to the command above. If the default value is not specified, the default value is null.
Arflags the parameters of the function Library Packager ar command. The default value is "rv". Asflags assembly language compiler parameters. (when obviously called ". S" or ".  S "file). CFLAGS C language Compiler parameters. Cxxflags C language compiler parameters.  Coflags the RCS command parameter. Cppflags C preprocessor parameters. (The C and Fortran compilers are also used). F, FLAGS Fortran language compiler parameter. GFLAGS SCCS "Get" program parameters. LDFLAGS the linker parameters. (e.g., "LD") lflags Lex Grammar Analyzer parameter. Pflags Pascal language compiler parameter. Rflags the Fortran compiler parameter of the RATFOR program. Yflags YACC Grammar Analyzer parameters.

Third, the definition of variables.

In makefile we define a series of variables, and when Makefile is executed, the variables are extended to the corresponding reference positions.

3.1 Environment variables defined in the environment Makefiles,make will make the values in this variable similar to the Include action. The values in this variable are other makefile, separated by a space. Unlike include, the makefile "target" from this environment change will not work, and if the file defined in the environment variable finds an error, make will ignore it. It is not recommended to use this environment variable, which is defined, and when you use make, all makefile will be affected by it.

3.2 General variables ("override" principle)

The variable declaration needs to be assigned the initial value, when used, to add the "$" symbol before the variable name, preferably "()" or "{}" to include the variable. To use the real "$" character, you need to indicate "$$".

There are 3 kinds: 1, the variable is assigned to a constant (VARs = PROGRAM.O foo.o utils.o), 2 variables are assigned to variables (variables can be defined using the following variables) (vars1 = $ (vars2)); 3 Variables are assigned variables (variables can only be defined using the preceding variables) (vars1: = $ (VARs)); 4 Assignment by criteria (assignment is not previously assigned) (VARS3 = $ (VARs))

Note: "=" and additional meaning. The variable is not defined before, "=" Automatically becomes "=", and if so, "=" inherits the assignment of the previous operation. If the previous is ": =", then "=" will be ": =" as its assignment.

As explained above: Makefile The first step is to establish a complete dependency diagram ("=" in the first step only establishes the relationship, ": =" in the first step of the value expansion)

The value of a variable starts with the first non-null character behind the definition of its ' = ' or ': = ', until the comment or line breaks. (space is defined as follows)

NullString: =

Space: = $ (nullstring) #end

3.3 Automatic variables

　　　　[email protected]: set of target files in the rule

　　　　$%: The goal in the rule is the set of function library files (if a target is "foo.a bar.o", then "$%" is "BAR.O", "[email protected]" is "FOO.A")

　　　　$<: The first dependency of a target in a rule depends on it. If the dependent target is defined in a pattern (that is, "%"), then "$<" will be a set of files conforming to the pattern (in fact one is taken out).

　　　　$?: the set of all new dependent targets in the rule that are more than the target.

　　　　$^: The collection of all dependent targets in the rule. separated by a space. If there are multiple duplicates in the dependent target, that variable will remove the duplicate dependent target and keep only one copy.

　　　　$: The collection of all dependent targets in the rule. Sameas "$^", except that it does not remove duplicate dependent targets.

　　　　$*: "%" in the target pattern in the rule and its previous section. If the target is "DIR/A.FOO.B" and the target's pattern is "a.%.b", then the value of "$*" is "Dir/a.foo".

Note: If there is no definition of the schema in the target, then "$*" cannot be deduced. if the suffix of the target file is recognized by make, then "$*" is the part of the suffix.

If the target is "foo.c", ". C" is the suffix name that make can recognize, and the value of "$*" is "foo". This feature is GNU make and may not be compatible with other versions of make, so try to avoid using "$*".

In the automatic quantitative quantities listed above. The four variables ([email protected], $<, $%, $*) only have one file in the extension, and the other three values are a list of files. These automation variables can also get the directory name of the file or the file name in the current directory in accordance with the schema, only need to match the word "D" or "F". This is the feature of the old version of GNU make, which we can do with the function "dir" or "Notdir" in the new version. The meaning of "D" is directory, that is, the meaning of "F" is file. Example:$ (@D) "Equals function" $ (notdir [email protected]) ". ,$ (@F)

3.4 Make command line setup parameters

　　　　If the variable is set by the command-line argument of make, then the assignment of the variable in makefile is ignored. To set the values of such parameters in makefile, you can use the "override" indicator. Its syntax is:

Override Para=value or override:p Ara=value

Example:

(1) Override Gao + = ABC (2) Gao + + ABC
All:all:
@echo $ (GAO) @echo $ (GAO)

Simultaneous execution: Make gao=12345 (1) The result is 12345 ABC; (2) The result is 12345

3.5 target variables and schema variables

The target variable sets a local variable for a target (the scope is only in this rule and in the rules and regulations, and does not affect the values of global variables other than the rule chain).

The pattern variable is that we can give a "pattern" that can be defined on all targets that conform to this pattern (make "mode" generally contains at least one "%").

　　　　　　target: PATA = g no matter what the global $ (PATA) value is, the prog target, and all the $ (CFLAGS) values that it throws are "-G".

%.o:pata=-O All values of $ (PATA) in the rule that match the end of [. O] are "-o".

3.6 Advanced usage of variables

1. The replacement variable has a partial, format: "$ (var:a=b)" or "${va:a=b}". Meaning: Replace All "A" in the variable "var" with "a" in the "a" string "End" ("trailing" i.e. "space" or "Terminator") with "B" string.

2. "Static mode" replacement. $ (VAL:%.O=%.C), which relies on the same pattern in the substituted string.

Iv. Documentation Instructions

1. Refer to another makefile in one makefile, just like the Include in C language

The way to reference other makefile files in makefile is to use Inclue filename.mk.

2. Specify a valid part of Makefile, as in the case of precompiled # if in C

"Function" is used with "conditional statement"

Ifdef

Do_sort Func: = sort

Else

Func: = Strip endif

Bar: = a d b g Q c

Foo: = $ ($ (func) $ (bar))

In this example, if "Do_sort" is defined, then $ (foo) means to sort% (bar). No "Do_sort" is defined, then% (foo) means calling the Strip function on bar.

3. There is a command to define multiple lines (define and Endef)

The define indicator is followed by the name of the variable, which works the same way as the "=" operator. The value of a variable can contain functions, commands, literals, or other variables. Because the command needs to start with the [tab] key, if the command variable you define with define does not start with the [tab] key, then make does not think of it as a command.

Define Two-lines
echo Foo
echo $ (BAR)
Endef

5, comments. Makefile is only a line comment, like the Unix shell script, its comments are "#" characters, if you want to use the "#" character in your makefile, you can escape with a backslash, such as: "\#".

Makefile Study Notes