Protection mode and its programming--interrupts and exception handling

Absrtact: In order to improve the efficiency of CPU utilization, we use interrupt policy to deal with some external events. At the same time, the software also needs to trigger some interrupts and exceptions, such as 0 interrupt/page fault exception. Interrupts and exceptions are often unpredictable compared to subroutine calls, and can significantly improve CPU productivity compared to interrupts/exceptions and polling. Interrupts occur at any moment, the corresponding hardware signals. Of course, the software can also generate interrupts through an int n instruction. This paper mainly explains the principle of service processing using interrupts, and the detailed process of interrupt processing.

1. Exception and interrupt vectors
Each exception and interrupt condition that needs to be specially handled by the processor is given a label called a vector, and the index range of the vector number is 0~255, where 0~31 is reserved and 32~255 is used for user-defined interrupts.

The exceptions and interrupts in protected mode are as follows:

Vector number	Mnemonic	Description	Type	Error number	Generate source
0	#DE	Except for errors	Fault	No	Div or idiv instructions
1	#DB	Debugging	Fault/Trap	No	Any code or data reference, or an int 1 instruction
2	--	NMI Interrupt	Interrupt	No	unshielded External interrupts
3	#BP	Breakpoint	Trap	No	INT 3 Instruction
4	#OF	Overflow	Trap	No	into command
5	#BR	Boundary Range exceeded	Fault	No	Bound directive
6	#UD	Invalid operation code (opcode not defined)	Fault	No	UD2 instruction or reserved opcode. (new directive added in Pentium Pro)
7	#NM	Device not present (no math coprocessor)	Fault	No	Floating-point or wait/fwait directives
8	#DF	Double error	abnormal termination	Have (0)	Any instruction that can produce an exception, NMI, or Intr
9	--	Coprocessor segment Transcendence (reserved)	Fault	No	Floating-point instruction (the CPU does not produce this exception after 386)
10	#TS	Invalid task status Segment TSS	Fault	Yes	Task Exchange or access to TSS
11	#NP	Segment does not exist	Fault	Yes	Load segment registers or access system segments
12	#SS	Stack segment Error	Fault	Yes	Stack operations and SS Register loading
13	#GP	General Protection Errors	Fault	Yes	Any memory references and other protection checks
14	#PF	Page error	Fault	Yes	Any memory reference
15	--	(Intel reserved, do not use)		No
16	#MF	x87 FPU floating point error (math error)	Fault	No	x87 FPU floating-point or wait/fwait directives
17	#AC	Check up on	Fault	Have (0)	A reference to any data in memory
18	#MC	Machine Check	abnormal termination	No	Error code (if any) and source associated with CPU type (Pentium processor introduction)
19	#XF	SIMD Floating-point exceptions	Fault	No	SSE and SSE2 floating point instructions (PIII processors introduced)
20-31	--	(Intel reserved, do not use)
32-255	--	User-defined (non-reserved) interrupts	Interrupt		external interrupt or int n instruction

2. Interrupts and exception sources 2.1 Interrupt Source

Processor accepts interrupts from two places: external (hardware-generated) interrupts
Software-generated interrupts

External interrupts are received by two pins (Intr and NMI) on the processor chip. Note that theNMI receives an unshielded interrupt, which uses a fixed interrupt number of 2. Other interrupts can be masked using the IF flag bit of the flag register.

2.2 Exception Source
The source of the exception received by the processor also has two
@@@ 处理器 detected an error exception
@@@ 软件-generated exceptions

Exceptions can be divided into faults, aborts, and traps in detail. int 0, int 3 (breakpoint exception), bound can produce an exception from the software. The INT n directive can be used for software simulation exceptions, but there is a limitation.

3. Exception classification

The

can be subdivided into faults (Fault), traps, and aborts (abort), depending on how the exception is reported and whether the exception's instructions can be re-executed. Fault: The exception that can be corrected, once corrected, the program can run correctly.
Trap: An exception that is reported immediately after an instruction that caused the trap is executed.
Abort is an exception that does not always cause an exact location of an exception's instruction.

4. Re-execution of the program or task
in order for the program to be able to resume execution after an exception or interrupt processing is complete, exceptions other than abort can report exact command locations, and all interrupts are guaranteed to occur on the instruction boundary.

for fault class exceptions, the returned pointer saved when the processor generates an exception points to an error instruction. For example, page failure instructions (think about how to do it). To ensure that re-execution is transparent to the current executing program, the processor holds the necessary registers and stack pointer information so that it can return to the state before the instruction error.

for Trap class exceptions, the returned pointer saved when the processor produces an exception points to the latter instruction that caused the trap operation. For example, when the JMP command executes, the exception is created, and after the exception is restored, it goes back to the target location that jmp refers to, not the next instruction in JMP. The

Abort class exception does not support the reliable re-execution of programs or tasks. The

Interrupt performs the execution of the interrupted program strictly without any loss of coherence.

5. Open and disable interrupts
The IF in EFlags can be used to suppress interrupts that can be masked, which can be set and understood by STI and CLI. These two instructions can be executed only when the program is CPL<=IOPL, or a general protective exception will be thrown. The IF flag is affected by the following operation.
1) Push and pop instructions: Push is used to press the EFlags stack, then can be modified, then pop
2) the task switch, Popf, iret instructions can be loaded eflags, so you can modify it.
3) processing an interrupt via an interrupt gate the IF flag is automatically cleared, thereby prohibiting the masking interrupt. If an interrupt is handled through a trap door, then the IF flag is not reset.

6. Priority of exception and interrupt handling

The processor will first handle the highest level of interrupts and exceptions, and the low-priority exceptions will be discarded, and the low-priority interrupts will be kept waiting. When the interrupt handler returns to the task, the discarded exception occurs again.

The priority of the exception or interrupt is as follows:

Vector number	Mnemonic	Description	Type	Error number	Generate source
0	#DE	Except for errors	Fault	No	Div or idiv instructions
1	#DB	Debugging	Fault/Trap	No	Any code or data reference, or an int 1 instruction
2	--	NMI Interrupt	Interrupt	No	unshielded External interrupts
3	#BP	Breakpoint	Trap	No	INT 3 Instruction
4	#OF	Overflow	Trap	No	into command
5	#BR	Boundary Range exceeded	Fault	No	Bound directive
6	#UD	Invalid operation code (opcode not defined)	Fault	No	UD2 instruction or reserved opcode. (new directive added in Pentium Pro)
7	#NM	Device not present (no math coprocessor)	Fault	No	Floating-point or wait/fwait directives
8	#DF	Double error	abnormal termination	Have (0)	Any instruction that can produce an exception, NMI, or Intr
9	--	Coprocessor segment Transcendence (reserved)	Fault	No	Floating-point instruction (the CPU does not produce this exception after 386)
10	#TS	Invalid task status Segment TSS	Fault	Yes	Task Exchange or access to TSS
11	#NP	Segment does not exist	Fault	Yes	Load segment registers or access system segments
12	#SS	Stack segment Error	Fault	Yes	Stack operations and SS Register loading
13	#GP	General Protection Errors	Fault	Yes	Any memory references and other protection checks
14	#PF	Page error	Fault	Yes	Any memory reference
15	--	(Intel reserved, do not use)		No
16	#MF	x87 FPU floating point error (math error)	Fault	No	x87 FPU floating-point or wait/fwait directives
17	#AC	Check up on	Fault	Have (0)	A reference to any data in memory
18	#MC	Machine Check	abnormal termination	No	Error code (if any) and source associated with CPU type (Pentium processor introduction)
19	#XF	SIMD Floating-point exceptions	Fault	No	SSE and SSE2 floating point instructions (PIII processors introduced)
20-31	--	(Intel reserved, do not use)
32-255	--	User-defined (non-reserved) interrupts	Interrupt		external interrupt or int n instruction

7. Interrupt Descriptor Descriptor

The interrupt Descriptor descriptor links Each exception or interrupt vector to their processing. is also 8B, unlike the GDT, its first item can contain descriptors. To make an index of an IDT table, the vector number is usually multiplied by 8. Because there are up to 256 interrupt vectors, you need up to 256 descriptors. All null descriptors in IDT need to have their presence bit 1.

The IDT table can be positioned anywhere in the linear address space using IDTR. The IDTR is a 32b register that contains a 32-bit base address and a 16b limit. The IDT table base address should be 8b aligned to speed up access.

Lidt and Sidt are used to load and save IDTR. Where Lidt can only be executed by cpl=0 code, Sidt may be executed at any privileged level.
If the IDT limit is exceeded, a general protective exception is generated.

8.IDT Descriptor

The IDT table holds three types of door descriptors: break doors, trap doors, and mission gates. They are all 8B, in the following format:

both the interrupt gate and the trap gate have a long pointer (segment selector and offset value)that is used to transfer the program to the interrupt or exception handling process, with the difference between the IF flag bit. The task gate and Gdt/ldt in IDT are described in the same format, and the task Gate descriptor contains a TSS segment selector, which is used to handle exceptions and interrupts.

9. Exception and interrupt handling

The processing method is similar to the call instruction procedure and task method. The interrupt or exception handling process is shown in the following figure.

The interrupt or exception handling process is as follows:
1) If the processing occurs at a high privilege level, then a stack switch operation will occur, the process of stack switching is as follows

A, the processor gets interrupted from the TSS segment of the currently executing task or the stack's segment selector and stack pointer used by the exception handling process. The stack selector and stack pointer of the interrupted task are then pressed into the new stack, as shown in the following figure.

B, the CPU will EFlags, CS, EIP current value also press into the new stack
C, if the exception produces an error number, then the error number will also be pressed into the new stack.
2) If the process and interrupt tasks are at the same privilege level
Then there will be no above step a
in order to return from the interrupt processing task, the process must use the Iret directive, because Iret restores eflags to the relevant registers compared to the RET directive. However, the EFlags iopl field is restored only when cpl=0, and the IF flag is changed only when CPL<=IOPL. If a stack switch occurs, the Iret will revert back to the original stack.

9.1 Exception or interrupt handling process protection

The privilege level protection mechanism of the

exception or interrupt handling process is similar to calling the normal procedure by calling the gate (that is, the interrupt or exception handling process does not take precedence.) ). The CPU does not transfer control to the interrupt process of a lower code segment than CPL, but there are also differences: @@@ 中断 or exception vectors are not RPL, so there is no corresponding check.
@@@ 只有 When interrupts are generated by int n, int 3, int 0, does the processor check for the interrupt or DPL in the trap door, and requires CPL<=DPL. This prevents the application from invoking important exception handling procedures, such as page fault handling, through software interrupts. For exceptions that the hardware and processor can detect, the processor ignores the interrupt or DPL in the trap door, such as a clock interrupt.

To achieve this goal, we typically use one of the following methods: The
@@@ 异常 or the interrupt handler is placed in a consistent code snippet-a technique that can be used to simply access the stack data (such as except for an error exception). If the handler needs to access the data in the data segment, then privilege level 3 must be able to access the data segment, so that reliance, there is no protection to say. Because the ~~~~~~~~
@@@ 处理 can be placed in non-conforming code with privileged level 0, this process can always be performed regardless of the current privilege level of the interrupted task or program.


9.2 Exceptions or how flags are used during interrupt handling the only difference between the break gate and the trap gate is that they are on the method of the IF flag bit on the processor operation EFlags-think about what it is.


9.3 Tasks that perform interrupt processing     access to the terminal or exception processing through the task gate in the IDT table will cause the task to switch. This allows the execution of interrupts or exception handling in a dedicated task. The task gate in the IDT table, referencing the TSS descriptor in the GDT table, interrupts the switch of the task to the same as the normal task, but this method is not used in the 0.12 kernel.

10. Interrupt Processing Task

A task switch is caused when the terminal or exception processing is accessed through the task gate in the IDT table. Using separate tasks to handle exceptions and interrupts has the following benefits @@@ 被 full context of the interrupted task is automatically saved
@@@ 处理 interrupts or exceptions, the new TSS allows the process to use the new privilege level 0 stack. In the event that the stack of the current privilege level 0 is corrupted, if an exception occurs and interrupts are present, the interrupt processing process through the task can effectively prevent the system from crashing if a new privilege level 0 stack condition is provided for the interrupt processing process.
@@@ 通过 separate address space by using a separate LDT to interrupt or exception handling tasks.

Use separate tasks to handle exceptions or outages-a large number of machine states need to be saved, interrupts are slow, and latency is high.

The interrupt processing task cut mechanism is shown in the following figure:

When an exception or interrupt handle task is used for the operating system, there are actually two mechanisms for dispatching tasks: hardware scheduling of operating system software and CPU interrupt mechanism. The use of software scheduling method to take into account the interruption at the beginning of the use of interrupt processing tasks.

11. Error code

When an exception condition is related to a specific segment, the processor presses an error code onto the stack of the exception-handling process. The error code and the segment selector are similar, but the lowest 3 bits are not the T1 and RPL fields, but the following three flags
EXT: External event flag
IDT: If the error code is set, the part points to a gate descriptor in IDT, and vice versa, to the segment descriptor
Tl: When idt= 0: Tl=1, indicating a descriptor in the LDT; tl=0, indicating the descriptor in the GDT

Index field: Indicates the index value of the segment or door descriptor. In some cases, the error code is all 0, indicating that the error was not caused by a particular segment, or that an empty segment descriptor was filled in. The error code format for the
page fault exception is different from the above, as shown in the following figure. Only the lowest three bits are useful, and their names are the same as the last three bits of the page table entry (u/s, W/R, P).
In addition, the CPU also puts the linear address that causes the page fault exception in the CR2, the page error exception handler can use this address to locate the related page catalog item and the page table item.

Note: The error is not automatically ejected from the stack by the iret instruction, so the interrupt handler must clear the error code on the stack before returning. In addition, although some exceptions generated by processing produce an error code and are automatically saved to the stack of processing, an external hardware interrupt or an exception generated by the program executing an int n instruction does not push the error code onto the stack.